JPS6462919A - Duty controlled pulse generating circuit - Google Patents

Duty controlled pulse generating circuit

Info

Publication number
JPS6462919A
JPS6462919A JP21983487A JP21983487A JPS6462919A JP S6462919 A JPS6462919 A JP S6462919A JP 21983487 A JP21983487 A JP 21983487A JP 21983487 A JP21983487 A JP 21983487A JP S6462919 A JPS6462919 A JP S6462919A
Authority
JP
Japan
Prior art keywords
output
decoder
signal
counter
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21983487A
Other languages
Japanese (ja)
Inventor
Akinori Akazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP21983487A priority Critical patent/JPS6462919A/en
Publication of JPS6462919A publication Critical patent/JPS6462919A/en
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Abstract

PURPOSE:To generate a duty control pulse with high accuracy by a digital element circuit by supplying an output of a clock signal counter to a duty ratio decoder and a frequency decoder to apply logic operation to outputs of both the circuits. CONSTITUTION:When a reset signal of a counter 1 changed from a low level to a high level and the reset state is released, and a clock signal is inputted for a prescribed period, the output of a binary counter 1 is increased synchronously with the clock signal. In such a case, a preset duty ratio and a decode value corresponding to the frequency are set to a duty ratio decoder 2 and a frequency decoder 3 in this case. When the output of the counter 1 is coincident with the decoded value or exceeds the decode value or goes down therefrom, the output of the decoders 2,3 is changed. The output signal A of the decoder 2 and the signal C being the result of 1/4 frequency division of the output signal B of the decoder 3 are ANDed by an AND circuit 5 to obtain an output D. Thus, the duty control pulse with high accuracy is generated.
JP21983487A 1987-09-02 1987-09-02 Duty controlled pulse generating circuit Pending JPS6462919A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21983487A JPS6462919A (en) 1987-09-02 1987-09-02 Duty controlled pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21983487A JPS6462919A (en) 1987-09-02 1987-09-02 Duty controlled pulse generating circuit

Publications (1)

Publication Number Publication Date
JPS6462919A true JPS6462919A (en) 1989-03-09

Family

ID=16741779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21983487A Pending JPS6462919A (en) 1987-09-02 1987-09-02 Duty controlled pulse generating circuit

Country Status (1)

Country Link
JP (1) JPS6462919A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100336756B1 (en) * 1999-09-08 2002-05-16 박종섭 Clock dividing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100336756B1 (en) * 1999-09-08 2002-05-16 박종섭 Clock dividing circuit

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