JPS5661850A - Synchronizing device - Google Patents

Synchronizing device

Info

Publication number
JPS5661850A
JPS5661850A JP13731679A JP13731679A JPS5661850A JP S5661850 A JPS5661850 A JP S5661850A JP 13731679 A JP13731679 A JP 13731679A JP 13731679 A JP13731679 A JP 13731679A JP S5661850 A JPS5661850 A JP S5661850A
Authority
JP
Japan
Prior art keywords
frame
phase
memory
time slot
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13731679A
Other languages
Japanese (ja)
Other versions
JPS5931264B2 (en
Inventor
Hideo Kuroda
Tokuhiro Kitami
Yukio Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP13731679A priority Critical patent/JPS5931264B2/en
Publication of JPS5661850A publication Critical patent/JPS5661850A/en
Publication of JPS5931264B2 publication Critical patent/JPS5931264B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To avoid the out-of-synchronism for the frame when the frame is detected, by securing a synchronization of the bit phase of the digital signal received a time-division multiplication on the transmission line and the frame phase with the integrated bit phase and the frame phase of a station. CONSTITUTION:The frame memory 18 stores the signal read out of the elastic memory 12 and then reads the signal in the reference bit timing to secure the frame phase synchronization. And the control circuit 26 detects that the write/read addresses of the memory 12 approximate more than the fixed value when the preamble time slot is received and then gives a jump to both the reading address of the memory 12 and the writing address of the memory 18 by the time slot number less than the preamble time slot number. Thus the bit phase of the digital signal received a time-division multiplication and the frame phase can be synchronized with the integrated bit phase and the frame phase of a station. As a result, the out- of-synchronism can be avoided for the frame when the frame is detected.
JP13731679A 1979-10-24 1979-10-24 synchronizer Expired JPS5931264B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13731679A JPS5931264B2 (en) 1979-10-24 1979-10-24 synchronizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13731679A JPS5931264B2 (en) 1979-10-24 1979-10-24 synchronizer

Publications (2)

Publication Number Publication Date
JPS5661850A true JPS5661850A (en) 1981-05-27
JPS5931264B2 JPS5931264B2 (en) 1984-08-01

Family

ID=15195827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13731679A Expired JPS5931264B2 (en) 1979-10-24 1979-10-24 synchronizer

Country Status (1)

Country Link
JP (1) JPS5931264B2 (en)

Also Published As

Publication number Publication date
JPS5931264B2 (en) 1984-08-01

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