JPS5773546A - Fixed delay insertion and removal memory circuit - Google Patents

Fixed delay insertion and removal memory circuit

Info

Publication number
JPS5773546A
JPS5773546A JP55149000A JP14900080A JPS5773546A JP S5773546 A JPS5773546 A JP S5773546A JP 55149000 A JP55149000 A JP 55149000A JP 14900080 A JP14900080 A JP 14900080A JP S5773546 A JPS5773546 A JP S5773546A
Authority
JP
Japan
Prior art keywords
fixed delay
removal
circuit
delay insertion
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55149000A
Other languages
Japanese (ja)
Inventor
Yuzo Fujii
Toshio Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55149000A priority Critical patent/JPS5773546A/en
Publication of JPS5773546A publication Critical patent/JPS5773546A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To prevent malfunction during frame synchronizing hunting under a simple control, by inhibiting the malfunction of fixed delay insertion and removal produced secondarily after fixed delay insertion and removal through the information of fixed delay insertion and removal and the information in frame synchronism hunting. CONSTITUTION:A fixed delay insertion and removal memory circuit X connected to a frame synchronism circuit 4 consists of a fixed delay element 1, selector 2, flip- flop 3, memory circuit 5, write address counter 6, read address counter 7 and phase comparison circuit 8. Further, a protection circuit Y consists of a leading detection circuit 9, and set/reset flip-flop 10. The protection circuit Y controls the operation of the phase comparison circuit 8 based on the information of the fixed delay insertion and removal and the information in the frame synchronism hunting and the insertion/removal of fixed delay is inhibited until the frame synchronism is established.
JP55149000A 1980-10-24 1980-10-24 Fixed delay insertion and removal memory circuit Pending JPS5773546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55149000A JPS5773546A (en) 1980-10-24 1980-10-24 Fixed delay insertion and removal memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55149000A JPS5773546A (en) 1980-10-24 1980-10-24 Fixed delay insertion and removal memory circuit

Publications (1)

Publication Number Publication Date
JPS5773546A true JPS5773546A (en) 1982-05-08

Family

ID=15465459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55149000A Pending JPS5773546A (en) 1980-10-24 1980-10-24 Fixed delay insertion and removal memory circuit

Country Status (1)

Country Link
JP (1) JPS5773546A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224528A (en) * 1985-03-29 1986-10-06 Oki Electric Ind Co Ltd Frame aligner

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61224528A (en) * 1985-03-29 1986-10-06 Oki Electric Ind Co Ltd Frame aligner
JPH0626328B2 (en) * 1985-03-29 1994-04-06 沖電気工業株式会社 Frame aligner device

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