JPS5475948A - Memory control system - Google Patents
Memory control systemInfo
- Publication number
- JPS5475948A JPS5475948A JP14275877A JP14275877A JPS5475948A JP S5475948 A JPS5475948 A JP S5475948A JP 14275877 A JP14275877 A JP 14275877A JP 14275877 A JP14275877 A JP 14275877A JP S5475948 A JPS5475948 A JP S5475948A
- Authority
- JP
- Japan
- Prior art keywords
- information
- loop
- address
- counter
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To quicken the leading after reconnection of power supply, by detecting the address information before the application of power supply, in the memory unit consisting of a plurality of first information loop of shift register memory and other second information loop.
CONSTITUTION: The n-th of the minor loop each is taken as the address memory, all "1" are written in arbitrary one minor loop in them, and addresses are memorized in the remaining address memory minor loop. In normal case, when the address represented by the loop counter 8 and the address signal A1 are in agreement, the readout of the information D1 is made with the operation signal C2. At the interruption of power supply, the information of the counter 8 is in volatile state, but "1" information is present at the location where the address information is present on the major loop 2. Accordingly, when the first "1" is detected after n sets of "0" are detected with the detection circuit 10, the address information A1 is fed to the counter 8 and set, returning the control to normal state.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52142758A JPS599101B2 (en) | 1977-11-30 | 1977-11-30 | Memory control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52142758A JPS599101B2 (en) | 1977-11-30 | 1977-11-30 | Memory control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5475948A true JPS5475948A (en) | 1979-06-18 |
JPS599101B2 JPS599101B2 (en) | 1984-02-29 |
Family
ID=15322881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52142758A Expired JPS599101B2 (en) | 1977-11-30 | 1977-11-30 | Memory control method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS599101B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58200492A (en) * | 1982-05-18 | 1983-11-22 | Seiko Epson Corp | Magnetic bubble memory device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4942246A (en) * | 1972-05-08 | 1974-04-20 | ||
JPS5063850A (en) * | 1973-10-03 | 1975-05-30 | ||
JPS5193832A (en) * | 1975-02-17 | 1976-08-17 | ||
JPS5239325A (en) * | 1975-09-22 | 1977-03-26 | Ibm | Method of retrieving frame synchronization of nonndestructive dynamic memory |
-
1977
- 1977-11-30 JP JP52142758A patent/JPS599101B2/en not_active Expired
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4942246A (en) * | 1972-05-08 | 1974-04-20 | ||
JPS5063850A (en) * | 1973-10-03 | 1975-05-30 | ||
JPS5193832A (en) * | 1975-02-17 | 1976-08-17 | ||
JPS5239325A (en) * | 1975-09-22 | 1977-03-26 | Ibm | Method of retrieving frame synchronization of nonndestructive dynamic memory |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58200492A (en) * | 1982-05-18 | 1983-11-22 | Seiko Epson Corp | Magnetic bubble memory device |
Also Published As
Publication number | Publication date |
---|---|
JPS599101B2 (en) | 1984-02-29 |
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