GB1289051A - - Google Patents

Abstract

1289051 Multiplex pulse signalling SIEMENS AG 29 Jan 1970 [30 Jan 1969] 4310/70 Heading H4L In an arrangement for compensating for variations in transmission time in a time division multiplex link between stations, in particular PCM exchanges, the incoming signals on link Le are supplied via sequentially operated switches Sel to Se4, controlled by signals from De, to stores ZSp1 to ZSp4 and sequentially read out by switches Sa1 to Sa4 controlled by signals from Da. The control signals from De are derived from a counter Ue controlled by a synchronizing device Syn from the incoming signals so that each switch Se1 to S34 is closed for the duration of a channel time slot. Similarly the control signals from Da are derived from a counter Ua controlled by a clock pulse generator Sg defining the channel time slots at the receiving station. A comparator Vgl has one input receiving the control signal for switch Se3 and the other input receiving the control signal for switch Sal, the output A, if required, being supplied to a control input of the generator Sg. The earliest time at which read-out of a store Zp can take place is immediately after the signal has been written in and the latest time is immediately before the write-in of a further signal. With normal operation a switch Sa is operated in the second time slot after the operation of the corresponding switch Se and this allows for some variation in the relative timing of the input and output switches before either of the above limits are reached. Should delay changes occur which would exceed these limits, the comparator Vg1 is introduced so that if switches Se3 and Sal do not operate simultaneously an error signal is produced to control the generator Sg or the counter Ue. Alternatively the control signal may be produced when the operation of the switches is outside two limiting positions.