JPS5661098A - Memory device possible for quick test - Google Patents

Memory device possible for quick test

Info

Publication number
JPS5661098A
JPS5661098A JP13684479A JP13684479A JPS5661098A JP S5661098 A JPS5661098 A JP S5661098A JP 13684479 A JP13684479 A JP 13684479A JP 13684479 A JP13684479 A JP 13684479A JP S5661098 A JPS5661098 A JP S5661098A
Authority
JP
Japan
Prior art keywords
block
data
buffer
register
blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13684479A
Other languages
Japanese (ja)
Inventor
Kazuhiro Iio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13684479A priority Critical patent/JPS5661098A/en
Publication of JPS5661098A publication Critical patent/JPS5661098A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To quicken the check of memory array, by writing in the test data and reading out it through one time access for write-in and readout.
CONSTITUTION: The device provides a buffer 2 in which k-block data are sequentially written in by taking n-byte as 1 block, memory array 1 simultaneously writing in and reading out the data in nk-byte at the same time, buffer 5 tentatively storing the data for k blocks share read out, and readout register 7 sequentially transferred one by one block. At test, the test data for one block share are written in all the blocks of the buffer 2 with one time access with a block selection circuit 8 commonly, the content of k-bit at the same bit location is compared among the blocks in the data for k-block's share from the buffer 5 with a readout control circuit 12, and the result of comparison is written in the register 7. Further, the presence of error can be checked 14 from the content of the register 7.
COPYRIGHT: (C)1981,JPO&Japio
JP13684479A 1979-10-23 1979-10-23 Memory device possible for quick test Pending JPS5661098A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13684479A JPS5661098A (en) 1979-10-23 1979-10-23 Memory device possible for quick test

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13684479A JPS5661098A (en) 1979-10-23 1979-10-23 Memory device possible for quick test

Publications (1)

Publication Number Publication Date
JPS5661098A true JPS5661098A (en) 1981-05-26

Family

ID=15184819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13684479A Pending JPS5661098A (en) 1979-10-23 1979-10-23 Memory device possible for quick test

Country Status (1)

Country Link
JP (1) JPS5661098A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03226684A (en) * 1990-02-01 1991-10-07 Nec Corp Test circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03226684A (en) * 1990-02-01 1991-10-07 Nec Corp Test circuit

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