JPS57109199A - Alternate memory check system - Google Patents

Alternate memory check system

Info

Publication number
JPS57109199A
JPS57109199A JP55186812A JP18681280A JPS57109199A JP S57109199 A JPS57109199 A JP S57109199A JP 55186812 A JP55186812 A JP 55186812A JP 18681280 A JP18681280 A JP 18681280A JP S57109199 A JPS57109199 A JP S57109199A
Authority
JP
Japan
Prior art keywords
memory
information
alternate
circuit
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55186812A
Other languages
Japanese (ja)
Other versions
JPS6051144B2 (en
Inventor
Kiyokatsu Iijima
Shozo Taniguchi
Takahiro Sakuraba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55186812A priority Critical patent/JPS6051144B2/en
Publication of JPS57109199A publication Critical patent/JPS57109199A/en
Publication of JPS6051144B2 publication Critical patent/JPS6051144B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To achieve effective test for alternate memory and alternate operation, by providing an information inverting circuit on an alternate memory write-in information bus and confirming the selection of content of alternate memory readout information bus at test. CONSTITUTION:After an arbitrary bit on a write-in information bus 1 is inverted from a normal state and written in a normal memory 2, the readout informtion of the memory 2 is checked at a circuit 8, and the error bit location is stored in an alternate bit location storage register 9. Next, the normal information is written in the memory 2, an inverting control line 16 turns on relating to the bit location stored in the register 9 and the inverted information is written in the alternate memory 7 through an alternate write-in information inverting circuit 15. At the readout state of the memories 2, 7, the information on a bus 11 is selected relating to the bit location stored in the register 9 and the error is detected at the circuit 8. Next, the line 16 and the circuit 15 are kept off to make readout/write-in for the memories 2, 7, allowing to confirm the normality of the memory 7.
JP55186812A 1980-12-26 1980-12-26 Alternate memory inspection method Expired JPS6051144B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55186812A JPS6051144B2 (en) 1980-12-26 1980-12-26 Alternate memory inspection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55186812A JPS6051144B2 (en) 1980-12-26 1980-12-26 Alternate memory inspection method

Publications (2)

Publication Number Publication Date
JPS57109199A true JPS57109199A (en) 1982-07-07
JPS6051144B2 JPS6051144B2 (en) 1985-11-12

Family

ID=16195016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55186812A Expired JPS6051144B2 (en) 1980-12-26 1980-12-26 Alternate memory inspection method

Country Status (1)

Country Link
JP (1) JPS6051144B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043760A (en) * 1983-08-19 1985-03-08 Fujitsu Ltd Test system of alternate memory control function

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043760A (en) * 1983-08-19 1985-03-08 Fujitsu Ltd Test system of alternate memory control function

Also Published As

Publication number Publication date
JPS6051144B2 (en) 1985-11-12

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