JPS5660064A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5660064A
JPS5660064A JP13684579A JP13684579A JPS5660064A JP S5660064 A JPS5660064 A JP S5660064A JP 13684579 A JP13684579 A JP 13684579A JP 13684579 A JP13684579 A JP 13684579A JP S5660064 A JPS5660064 A JP S5660064A
Authority
JP
Japan
Prior art keywords
gate
window
implanted
film
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13684579A
Other languages
Japanese (ja)
Inventor
Takehide Shirato
Yoshiharu Nishimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13684579A priority Critical patent/JPS5660064A/en
Publication of JPS5660064A publication Critical patent/JPS5660064A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8236—Combination of enhancement and depletion transistors

Abstract

PURPOSE:To simplify the steps of manufacturing the semiconductor device by conducting the introduction of impurity by a special method, thereby raising the withstand voltage at a part of enhancement type and depletion type transistor and forming them on the same semiconductor substrate. CONSTITUTION:A field oxide film 4 for isolating respective transistors is formed on the surface of a P type silicon semiconductor substrate 2, the surface of the substrate 2 is oxidized, a gate oxide film 6 is formed thereon, and boron ion is implanted to the whole surface through the film 6. Then, a resist 10 is coated on the film 6, with a mask it is patterned by a photographic process, and there are formed the window 30 for D-Tr gate, the window 32 for off-set gate of high withstand E-Tr and window 34 for control and off-set gate of the high withstand voltage D-Tr. Then, phosphorus ion is implanted through the respective windows, surface layers 36, 38, 40 are thus formed, and drain current controlling and off-setting gate impurities are simultaneously implanted.
JP13684579A 1979-10-23 1979-10-23 Manufacture of semiconductor device Pending JPS5660064A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13684579A JPS5660064A (en) 1979-10-23 1979-10-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13684579A JPS5660064A (en) 1979-10-23 1979-10-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5660064A true JPS5660064A (en) 1981-05-23

Family

ID=15184841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13684579A Pending JPS5660064A (en) 1979-10-23 1979-10-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5660064A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6251248A (en) * 1985-08-30 1987-03-05 Toshiba Corp Manufacture of semiconductor device
JPS62123763A (en) * 1985-11-22 1987-06-05 Nec Corp Manufacture of semiconductor device
JP2007158105A (en) * 2005-12-06 2007-06-21 Matsushita Electric Ind Co Ltd Integrated circuit and manufacturing method therefor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5347278A (en) * 1976-10-12 1978-04-27 Toshiba Corp Insulated gate type field effect transistor
JPS53121583A (en) * 1977-03-31 1978-10-24 Toshiba Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5347278A (en) * 1976-10-12 1978-04-27 Toshiba Corp Insulated gate type field effect transistor
JPS53121583A (en) * 1977-03-31 1978-10-24 Toshiba Corp Manufacture of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6251248A (en) * 1985-08-30 1987-03-05 Toshiba Corp Manufacture of semiconductor device
JPH0321100B2 (en) * 1985-08-30 1991-03-20 Tokyo Shibaura Electric Co
JPS62123763A (en) * 1985-11-22 1987-06-05 Nec Corp Manufacture of semiconductor device
JP2007158105A (en) * 2005-12-06 2007-06-21 Matsushita Electric Ind Co Ltd Integrated circuit and manufacturing method therefor

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