JPS5650513A - Arrangement of semiconductor chip - Google Patents

Arrangement of semiconductor chip

Info

Publication number
JPS5650513A
JPS5650513A JP12764779A JP12764779A JPS5650513A JP S5650513 A JPS5650513 A JP S5650513A JP 12764779 A JP12764779 A JP 12764779A JP 12764779 A JP12764779 A JP 12764779A JP S5650513 A JPS5650513 A JP S5650513A
Authority
JP
Japan
Prior art keywords
wafer
mask
semiconductor
chip
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12764779A
Other languages
Japanese (ja)
Inventor
Masahiko Denda
Natsuo Tsubouchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12764779A priority Critical patent/JPS5650513A/en
Publication of JPS5650513A publication Critical patent/JPS5650513A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To facilitate the alignment of a mask for the manufacture of a semiconductor element and a semiconductor wafer by a method wherein a semiconductor chip to be arranged on the mask and the wafer is so arranged as to be symmetrical against the rotation of a specified angle. CONSTITUTION:When a semiconductor chip 2 is to be arranged on a mask 1 for the manufacture of a semiconductor element (or a semiconductor wafer), the chip is arranged at the position symmetrical against the rotation of 90 deg. (the characters ''DEN'' indicate the lower side of the chip). Accordingly, the relative positional relation of the mask and the wafer against the 90 deg. rotation of the wafer can be held in constant, and the alignment can be performed easily.
JP12764779A 1979-10-02 1979-10-02 Arrangement of semiconductor chip Pending JPS5650513A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12764779A JPS5650513A (en) 1979-10-02 1979-10-02 Arrangement of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12764779A JPS5650513A (en) 1979-10-02 1979-10-02 Arrangement of semiconductor chip

Publications (1)

Publication Number Publication Date
JPS5650513A true JPS5650513A (en) 1981-05-07

Family

ID=14965260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12764779A Pending JPS5650513A (en) 1979-10-02 1979-10-02 Arrangement of semiconductor chip

Country Status (1)

Country Link
JP (1) JPS5650513A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5641960A (en) * 1994-01-13 1997-06-24 Fujitsu Limited Circuit pattern inspecting device and method and circuit pattern arrangement suitable for the method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5641960A (en) * 1994-01-13 1997-06-24 Fujitsu Limited Circuit pattern inspecting device and method and circuit pattern arrangement suitable for the method

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