JPS5644952A - Micro processor - Google Patents

Micro processor

Info

Publication number
JPS5644952A
JPS5644952A JP12161879A JP12161879A JPS5644952A JP S5644952 A JPS5644952 A JP S5644952A JP 12161879 A JP12161879 A JP 12161879A JP 12161879 A JP12161879 A JP 12161879A JP S5644952 A JPS5644952 A JP S5644952A
Authority
JP
Japan
Prior art keywords
timing
output
program counter
output terminal
internal register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12161879A
Other languages
Japanese (ja)
Other versions
JPS6148189B2 (en
Inventor
Toshiaki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12161879A priority Critical patent/JPS5644952A/en
Publication of JPS5644952A publication Critical patent/JPS5644952A/en
Publication of JPS6148189B2 publication Critical patent/JPS6148189B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE: To improve development efficiency of programs, by providing a means, which uses the access timing of the instruction decoder to output the internal register value to the output terminal of the program counter, and a means which selects the internal register above.
CONSTITUTION: Clock Sϕ is the timing to latch instruction code (a) of the addressed user program into instruction register 3, and clock S3 is the timing to output program counter value (b) to the external. It is sufficient if the program counter value to output terminal 6 is output only during the timing of S3 and Sϕ. Consequently, the internal register value can be output at the timing of S1 and S2 through the data bus from program counter output terminal 6 during the access time of the instruction decoder by gates 35 and 36.
COPYRIGHT: (C)1981,JPO&Japio
JP12161879A 1979-09-21 1979-09-21 Micro processor Granted JPS5644952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12161879A JPS5644952A (en) 1979-09-21 1979-09-21 Micro processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12161879A JPS5644952A (en) 1979-09-21 1979-09-21 Micro processor

Publications (2)

Publication Number Publication Date
JPS5644952A true JPS5644952A (en) 1981-04-24
JPS6148189B2 JPS6148189B2 (en) 1986-10-23

Family

ID=14815705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12161879A Granted JPS5644952A (en) 1979-09-21 1979-09-21 Micro processor

Country Status (1)

Country Link
JP (1) JPS5644952A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60146341A (en) * 1984-01-09 1985-08-02 Nec Corp Microprocessor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60146341A (en) * 1984-01-09 1985-08-02 Nec Corp Microprocessor
JPH0330173B2 (en) * 1984-01-09 1991-04-26

Also Published As

Publication number Publication date
JPS6148189B2 (en) 1986-10-23

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