JPS5643739A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS5643739A
JPS5643739A JP11968479A JP11968479A JPS5643739A JP S5643739 A JPS5643739 A JP S5643739A JP 11968479 A JP11968479 A JP 11968479A JP 11968479 A JP11968479 A JP 11968479A JP S5643739 A JPS5643739 A JP S5643739A
Authority
JP
Japan
Prior art keywords
layer
type
island region
epitaxial layer
unified
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11968479A
Other languages
Japanese (ja)
Other versions
JPS6119112B2 (en
Inventor
Kazutoshi Nagano
Kosei Kajiwara
Kosuke Yasuno
Seiji Onaka
Tatsunori Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11968479A priority Critical patent/JPS5643739A/en
Publication of JPS5643739A publication Critical patent/JPS5643739A/en
Publication of JPS6119112B2 publication Critical patent/JPS6119112B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To remove a stress concentration in an interface between an island region and an isolation by a method wherein an insulating film that unified with the insulator is provided on a surface of an island region of the semiconductor device with an island region which isolated a bottom and a side phases by a porous oxidation. CONSTITUTION:A boron is injected to the surface of an N type Si substrate 21 to form a P type layer 31, an N type epitaxial layer 32 is formed thereupon. An SiO2 layer mask 33 is arranged on the surface of the epitaxial layer, and the boron is selectively diffused, and after the P type isolation region 34 to be reached to the P type layer 31 is formed, the mask 33 is removed to form the P type layer 35 throughout the surface of the epitaxial layer. The said substrate is doped in a hydrofluoric aqueous solution to perform an anodizing while performing the light illumination and the P type portion is converted to the porosity layer 37-39 and oxidized thereof, the unified SiO2 layer 22-24 are formed. In this way, the completely isolated island region 25 without the stress concentration can be readily formed.
JP11968479A 1979-09-17 1979-09-17 Semiconductor device and manufacture thereof Granted JPS5643739A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11968479A JPS5643739A (en) 1979-09-17 1979-09-17 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11968479A JPS5643739A (en) 1979-09-17 1979-09-17 Semiconductor device and manufacture thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP5868085A Division JPS60242636A (en) 1985-03-22 1985-03-22 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5643739A true JPS5643739A (en) 1981-04-22
JPS6119112B2 JPS6119112B2 (en) 1986-05-15

Family

ID=14767482

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11968479A Granted JPS5643739A (en) 1979-09-17 1979-09-17 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5643739A (en)

Also Published As

Publication number Publication date
JPS6119112B2 (en) 1986-05-15

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