JPS564060A - Digital equalizer - Google Patents

Digital equalizer

Info

Publication number
JPS564060A
JPS564060A JP7911979A JP7911979A JPS564060A JP S564060 A JPS564060 A JP S564060A JP 7911979 A JP7911979 A JP 7911979A JP 7911979 A JP7911979 A JP 7911979A JP S564060 A JPS564060 A JP S564060A
Authority
JP
Japan
Prior art keywords
supplied
counted
circuit
latch circuit
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7911979A
Other languages
Japanese (ja)
Other versions
JPH0252225B2 (en
Inventor
Yoshihisa Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Atomic Industry Group Co Ltd
Original Assignee
Nippon Atomic Industry Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Atomic Industry Group Co Ltd filed Critical Nippon Atomic Industry Group Co Ltd
Priority to JP7911979A priority Critical patent/JPS564060A/en
Publication of JPS564060A publication Critical patent/JPS564060A/en
Publication of JPH0252225B2 publication Critical patent/JPH0252225B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Measurement Of Current Or Voltage (AREA)
  • Measurement Of Radiation (AREA)

Abstract

PURPOSE: To effectively prevent the deterioration of the differential linearity due to a channel scaler, by outputting data as a cumulative value by the channel scaler.
CONSTITUTION: A clock signal 1 is counted by a binary counter U1, and counted values from the counter U1 are supplied successively to a latch circuit U2. When the following counting is started, a clear signal 2 is generated and supplied to the latch circuit U2 and a carry circuit U3. As a result, a preceding counted value is outputted from the latch circuit U2 as a complement, which is supplied to an adder U4. A cumulative value based on values obtained in the preceding and following counting is supplied from U1WU2, and also to U4 at once as a radix input. In U4, the complement input and radix input are added up, and an output is generated, which is representative of data based on the subtraction of the preceding counted value from present counted value. The data are stored in a buffer circuit U5 by a store signal and sent to a memory circuit.
COPYRIGHT: (C)1981,JPO&Japio
JP7911979A 1979-06-25 1979-06-25 Digital equalizer Granted JPS564060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7911979A JPS564060A (en) 1979-06-25 1979-06-25 Digital equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7911979A JPS564060A (en) 1979-06-25 1979-06-25 Digital equalizer

Publications (2)

Publication Number Publication Date
JPS564060A true JPS564060A (en) 1981-01-16
JPH0252225B2 JPH0252225B2 (en) 1990-11-09

Family

ID=13681029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7911979A Granted JPS564060A (en) 1979-06-25 1979-06-25 Digital equalizer

Country Status (1)

Country Link
JP (1) JPS564060A (en)

Also Published As

Publication number Publication date
JPH0252225B2 (en) 1990-11-09

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