JP3185341B2 - counter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter for counting the length of user data in a received packet.

[0002]

2. Description of the Related Art FIG. 4 shows a configuration of a conventional counter for counting the length of user data. In FIG.
Is an M-sequence counter that counts the length of user data in a received packet, and 22 is an initial value register that holds the value of the M-sequence counter 21 at the start of packet reception.
The output terminal Q of the M series counter 21 is an initial value register 2
2, the output terminal D of the initial value register 22 is connected to the load terminal LD1 of the M-sequence counter 21. 23 is an M-sequence subtractor that outputs a value obtained by subtracting the length of the trailer for the frame inspection sequence of the packet from the counter value of the M-sequence counter 21;
The input terminal IN of the M-sequence subtractor 23 is connected to the output terminal Q of the M-sequence counter 21 and the output terminal OUT is connected to the load terminal LD0 of the M-sequence counter 21.

FIG. 7 shows a format of a received packet, which is composed of user data and a trailer having a fixed length a. The trailer is a octets from the end of the packet. Note that F is a start flag and an end flag, which are also used for frame synchronization between transmission and reception.

FIG. 8 shows an example of the configuration of the M-sequence counter 21. The M-sequence counter includes, for example, shift registers 21a to 21d cascaded in four stages, an exclusive NOR gate 21e having two inputs of an uppermost stage, an output, and an output of a lowermost stage, and an output of the uppermost stage. Consists of Compared with a binary counter, this 4-bit M-sequence counter is often used because its hardware scale is small and high-speed operation is possible.

FIG. 9 shows a configuration example of the M-sequence subtractor 23. This M-sequence subtractor includes a large number (15) of inhibit AND gates 23a for inputting an M-sequence counter value.
And a plurality of (four) OR gates 23b to which a predetermined number of outputs in the inhibit AND gate 23a are input.

Next, the operation of the counter configured as described above will be described with reference to the timing charts shown in FIGS. FIGS. 5 and 6 show an example in which the user data length of a packet having a trailer length a of 4 bits is counted by a 4-bit M-sequence counter.

First, the operation when a normal packet composed of user data and a trailer is received will be described with reference to FIG.
Will be described with reference to FIG.

When a packet is received, the counter value 205 of the M-sequence counter 21 is stored in the initial value register 22 by the packet head signal 201 shown in FIG. Hold. FIG.
(G) indicates the initial value register value held in the register 22. Thereafter, the up input terminal U of the M-sequence counter 21
When the packet reception signal 202 is input to P at the timing shown in FIG. 5B, the counter value of the M-sequence counter 21 increases by one each time a packet is received, and the counter value becomes as shown in FIG. Changes to

When the reception of the packet is completed, the packet end signal 203 is input to the input terminal EN0 of the M-sequence counter 21.
Is input at the timing shown in FIG.
The subtraction value 206 output from the series subtractor 23 is loaded into the M series counter 21. By this operation, the counter value for the trailer can be subtracted from the M-sequence counter value 205. FIG. 5F shows a subtraction value of the subtractor 23 corresponding to the M-sequence counter value 205.

Next, the operation when an abnormal packet having a length equal to or less than the trailer length is received will be described with reference to the timing chart of FIG.

When a packet is received and the packet head signal 201 is input to the input terminal EN of the initial value register 22 at the timing shown in FIG. 6A, the value 205 of the M-sequence counter 21 is changed to the initial value register value. Is held in the initial value register 22. Thereafter, the value of the M-sequence counter 21 is incremented by one by the packet reception signal 202 every time a packet is received. Here, when the abnormal packet signal 204 is input to the input terminal EN1 of the M-sequence counter 21 at the timing shown in FIG. 6D, the bit sequence of the bit string shown in FIG. The value 207 is loaded into the M-sequence counter 21. This gives M
The sequence counter value 205 can be returned to the value before receiving the abnormal packet.

As described above, the conventional counter can also count the length of the user data in the received packet.

[0013]

However, in the above-mentioned conventional counter, since the counter value of the M-sequence counter used for the counter does not change regularly, the subtractor cannot be simply constructed. Therefore, the M-sequence subtractor used in the conventional counter must be constituted by a decoding circuit that outputs a subtraction result when an M-sequence counter value is input. However, when the M-sequence subtractor is constituted by a decoding circuit, there is a problem that the amount of hardware increases.

An object of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a counter in which the amount of hardware for M-sequence subtraction is reduced.

[0015]

In order to achieve the above object, the present invention provides a subtraction shift register in place of the conventional M-sequence subtracter, and sequentially subtracts the least significant bit of the M-sequence counter. By inputting to the shift register,
The subtraction shift register holds the subtraction result, and the subtraction result can be obtained only by referring to the subtraction shift register.

[0016]

According to the present invention, a value obtained by subtracting the trailer length from the value of the M-sequence counter can be obtained only by referring to the subtraction shift register. Has the effect of reducing

[0017]

FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, 1 is an M-sequence counter for counting the length of a received packet, 2 is an initial value register for holding an M-sequence counter value at the start of packet reception, and the input terminal D of this initial value register 2 is M The output terminal Q of the series counter 7 is connected to the output terminal Q of the M series counter 1. Reference numeral 3 denotes a shift register for subtraction. The input terminal D is connected to the M-sequence counter 1, and the output terminal Q is connected to the load terminal LD0 of the M-sequence counter 1.

Next, the operation of the above embodiment will be described with reference to FIG.
This will be described with reference to the timing chart of FIG. 2 and 3
Is an example in which the user data length of a packet having a trailer length of 4 bits is counted by a 4-bit M-sequence counter.

First, the operation when a normal packet composed of user data and a trailer is received will be described with reference to FIG.

When a packet is received, the counter value 105 of the M-sequence counter 21 is stored in the initial value register 2 by the packet head signal 101 shown in FIG. Hold. FIG.
(G) shows the initial value register value held in the register 2. Thereafter, the up input terminal UP of the M-sequence counter 1
When the packet reception signal 102 is input at the timing shown in FIG. 2B, the count value of the M-sequence counter 1 increases by one each time a packet is received.
It changes as shown in (e). At this time, the least significant bit of the M-sequence counter 1 is output to the subtraction shift register 3.

When the reception of the packet is completed, the packet end signal 103 is input to the input terminal EN0 of the M-sequence counter 1 at the timing shown in FIG. The subtraction shift register value 106 is loaded into the M-sequence counter 1. As a result, the packet length for the trailer is subtracted from the M-sequence counter value, and the user data length can be counted. FIG.
(F) shows the value of the shift register for subtraction 3 corresponding to the M-sequence counter value.

Next, the operation when an abnormal packet below the trailer is received will be described with reference to the timing chart of FIG.

When a packet head signal 101 is input to the input terminal EN of the initial value register 2 at the timing shown in FIG.
Is held in the initial value register 2 as the initial value register value. Thereafter, each time a packet is received, the reception signal 1
02 increments the value of the M-sequence counter 1 by one. Here, when the abnormal packet signal 104 is input to the input terminal EN1 of the M-sequence counter 1 at the timing shown in FIG. 3D, it is held in the initial value register 2 as shown in FIG.
Are loaded into the M-sequence counter 1. As a result, the M-sequence counter value 105 can be returned to the value before receiving the abnormal packet.

As described above, according to the above-described embodiment, the counter for counting the packet length of the received packet can be realized with a smaller hardware scale than the conventional counter.

[0025]

According to the present invention, as is apparent from the above embodiment, the amount of hardware for M-sequence subtraction can be reduced by configuring the M-sequence subtractor with a shift register, and the M-sequence subtraction can be performed in a received packet. The hardware scale of the counter for counting the user data length can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a counter according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation when a normal packet is received in one embodiment of the present invention.

FIG. 3 is a timing chart for explaining an operation when an abnormal packet is received in one embodiment of the present invention.

FIG. 4 is a configuration diagram of a conventional counter.

FIG. 5 is a timing chart for explaining the operation of a conventional counter when a normal packet is received.

FIG. 6 is a timing chart for explaining the operation of a conventional counter when an abnormal packet is received.

FIG. 7 is a configuration diagram of a received packet.

FIG. 8 is a diagram illustrating a configuration example of an M-sequence counter;

FIG. 9 is a diagram showing a configuration example of a conventional M-sequence subtractor.

[Explanation of symbols]

 1 M-sequence counter 2 Initial value register 3 Subtraction shift register 21 M-sequence counter 22 Initial value register 23 M-sequence subtracter 101 Packet head signal 102 Packet reception 103 Packet end signal 104 Abnormal packet reception signal 105 M-sequence counter value 106 Shift register value for subtraction 107 Initial value register value 201 Packet head signal 202 Packet reception signal 203 Packet end signal 204 Abnormal packet reception signal 205 M-sequence counter value 206 Subtraction value 207 Initial value register value

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 29/08 H04L 12/56 H03K 23/00

Claims (1)

(57) [Claims] 1. A counter for receiving a packet composed of user data and a trailer, counting a user data length in the received packet, an M-sequence counter for counting the user data length, and when starting packet reception. A counter for initial value holding the count value of the M series, and a shift register for subtraction which outputs a value obtained by subtracting a certain value from the count value of the M series counter.