JP2000216761A - Demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the operation of a demodulator side from becoming unstable due to fluctuation in the frequency of an extracted reception clock accordingly, when the signal waveform of a received biphasic code signal is disturbed in a conventional demodulation circuit for a biphase code signal, where a clock signal included in a received biphase code signal is extracted and the extracted clock signal is used as a received clock signal so as to demodulate data. SOLUTION: This demodulation circuit consists of a clock signal generator 1, that generates a clock signal with a frequency 16 times the bit rate of a received biphase code signal, a filter circuit 2 that eliminates noise, an edge detection circuit 3 that detects changes in the level of the biphase code signal, a sampling timing correction circuit 4 that decides a data fetching position, an FIFO memory 5, a read control circuit 6 that reads data stored in the FIFO memory 5 with a prescribed period, and a code conversion circuit 7 that converts the biphasic code signal into an NRZ code signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a demodulation circuit, and more particularly to a demodulation circuit for a biphase code signal.

[0002]

2. Description of the Related Art A demodulation circuit or a demodulation method of a biphase code signal is well known. For example, "Reception detection circuit device for serial communication device using bi-phase code" in JP-A-8-84161, "Bi-phase signal demodulation method" in JP-A-64-71326, and JP-A-63-84161. 268
No. 314, "Demodulation device", Japanese Patent Application Laid-Open No. 7-95188, "Asynchronous Digital Communication Method and Device", and Japanese Patent Application Laid-Open No. 63-104525, "Digital Modulation / Demodulation Circuit".

In each of these prior arts, a clock component is extracted from a biphase code signal, and this is used as a received clock signal on the demodulation circuit side.

This prior art has the advantage that the received data can be reliably reproduced, but on the other hand, when there is a signal waveform distortion, noise, or a change in the bit rate that occurs during data transmission, the received clock signal to be extracted is changed. There is a disadvantage that the frequency fluctuates. For this reason, the signal width of the NRZ code signal reproduced using the received clock also fluctuates, and the signal processing on the demodulation side becomes unstable. In particular, in the case of a synchronous circuit in which the extracted reception clock is used as the operation clock on the demodulation side, since a series of processing is performed following the fluctuating operation clock, a device that requires a pulse having a signal width of a certain time is required. For example, when the signal is used on the demodulation side, the above-described phenomenon may cause unstable operation on the demodulation side.

[0005]

There is a need to improve the operation of the demodulation side which depends on the stability of the reception clock when the clock signal extracted from the bi-phase code signal is used as the reception clock of the demodulation side.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a demodulation circuit for a bi-phase code signal having a high stability while keeping the demodulation operation speed of the bi-phase code signal constant.

[0007]

In order to solve the above-mentioned problems, the demodulation circuit according to the present invention employs the following characteristic configuration.

(1) An edge detection circuit for detecting a change point of an input signal level, a sampling timing correction circuit for correcting a sampling timing of the input signal based on an edge detection signal of the edge detection circuit, and the sampling timing correction circuit And a FIFO memory for storing the input signal based on the write pulse and reading the input signal at a constant period.

(2) The demodulation circuit according to (1), wherein a noise filter for removing noise of the input signal is provided at a stage preceding the edge detection circuit.

(3) The demodulation circuit according to (1) or (2), wherein the input signal is a biphase code signal.

(4) The demodulation circuit according to (3), further comprising a code conversion circuit for converting the data read from the FIFO memory into an NRZ code signal.

(5) The demodulation circuit according to (2), wherein the filter circuit comprises a plurality of cascade-connected D flip-flops, AND gates, inverters and JK flip-flops.

(6) The demodulation circuit according to any one of (1) to (5), wherein the edge detection circuit comprises a D flip-flop and an EX-OR gate.

(7) The demodulation circuit according to any one of the above (1) to (6), wherein the sampling timing correction circuit comprises a write pulse generator and a counter.

(8) A clock signal generator, a filter circuit for removing noise of an input signal, an edge detection circuit for detecting an edge of an output signal of the filter circuit, and an edge detection signal of the edge detection circuit A sampling timing correction circuit for correcting timing, a FIFO memory for taking in output data of the filter circuit at an output of the sampling timing correction circuit, and periodically reading data stored in the FIFO memory with a clock signal of the clock signal generator A demodulation circuit including a read control circuit.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a demodulation circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a preferred embodiment of a demodulation circuit according to the present invention. This demodulation circuit includes a clock signal generator 1, a filter circuit 2, an edge detection circuit 3,
It comprises a sampling timing correction circuit 4, a FIFO (first in first out) memory 5, a read control circuit 6, and a code conversion circuit 7.

The clock signal generator 1 generates a clock signal necessary for the above-described components to operate. The filter circuit 2 removes noise from the input biphase code signal. The edge detection circuit 3 detects a change (edge) in the signal level. The sampling timing correction circuit 4 controls the sampling timing of the input signal. The FIFO memory 5 stores (stores) data sampled by the sampling circuit. The read control circuit 6 controls data read from the FIFO memory 5.
The code conversion circuit 7 has an NRZ (non-return-t
(o-zero: non-zero return) Code conversion is performed.

In the demodulation circuit shown in FIG. 1, a clock signal generator 1 generates and uses a clock signal having a frequency 16 times the bit rate of the input biphase code signal as an operation clock. Input data is input to the filter circuit 2
Then, the edge detection circuit 3 detects a change point of the signal level. By utilizing the change in the signal level detected by the edge detection circuit 3, the sampling timing of the input data is changed and stored in the FIFO memory 5 asynchronously. Next, data is periodically read from the FIFO memory 5 and code conversion is performed by the code conversion circuit 7 to obtain the NRZ.
A code signal is obtained.

FIG. 2 is a detailed block diagram of the sampling timing correction circuit 4 in the demodulation circuit of FIG. The sampling timing correction circuit 4 includes a write (write) pulse generator 8 and a counter 9.
To the clock terminals of the write pulse generator 8 and the counter 9, a clock signal S1 having a frequency 16 times the bit rate of the input biphase code signal is generated by the clock signal generator 1 and input. The edge detection signal S11 from the edge detection circuit 3 is input to the ED end of the write pulse generator 8. A write control signal S12 is output from the W (write) end of the write pulse generator 8. Further, the output signal S20 from the LD end of the write pulse generator 8 is input to the LD end of the counter 9, and the output signal S21 from the CY end of the counter 9 is input to the CY end of the write pulse generator 8.

Next, a more detailed description will be given with reference to FIGS. The filter circuit 2 includes four D flip-flops, an AND gate, an inverter (inverting circuit), and a JK flip-flop. The input signal S2 is input to the first-stage D flip-flop and the AND gate. Further, output signals S3, S4, S5 of each D flip-flop
And S6 are also input to the AND gate.

The output signal S6 of the last stage D flip-flop is inverted by an inverter, and S8 is input to the K terminal of the JK flip-flop, and the output signal S7 of the AND gate is input to the J terminal of the JK flip-flop. . As a result, the output signal S9 from the JK flip-flop is a signal from which noise superimposed on the input signal S2 has been removed.
This assists the edge detection circuit 3 connected to the next stage, and prevents malfunction or instability due to edge detection due to noise.

FIG. 4 is a timing chart for explaining the operation of the filter circuit 2 of FIG. In FIG.
(A), (B), (C), (D), (E), (F),
(G), (H) and (I) show output signals S1, S2, S3, S4, S5, S6,
S7, S8 and S9 are shown. As understood from the timing chart of FIG. 4, even when the input signal S2 contains noise, the noise is removed from the output signal S9.

Next, the bi-phase code signal S9 from which noise has been removed by the filter circuit 2 is supplied to the edge detection circuit 3 and the FI
Input to the FO memory 5. FIG. 3 shows an example of a biphase code signal. Regardless of the sequence of input data, a change point in signal level always occurs once per bit. In other words, one edge occurs per bit. In the present invention, utilizing this characteristic, the sampling timing of input data is changed,
The data is stored in the O memory 5 and is periodically demodulated into an NRZ code signal by reading data from the FIFO memory 5.

When the bi-phase code signal S9 from which noise has been removed by the filter circuit 2 is input to the edge detection circuit 3, the edge (change) at which the signal S9 changes from the L level to the H level or from the H level to the L level. Point)
An edge detection signal S11 is output. The edge detection circuit 3 includes a D flip-flop and an EX-OR gate (exclusive OR). Bi-phase code signal S9
Is input to a D flip-flop, and the output signal S10 and the above-described bi-phase code signal S9 are input to an EX-OR gate to obtain an edge detection signal S11.

FIG. 5 is a timing chart for explaining the operation of the edge detection circuit 3. In FIG. 5, (A),
(B), (C) and (D) show clock signals S1,
A bi-phase code signal S9, an output signal S10 of the D flip-flop, and an edge detection signal S11.

Next, the sampling timing correction circuit 4
Has a configuration shown in FIG. 2 and generates a write pulse S12 for writing into the FIFO memory 5 based on the edge detection signal S11 detected by the edge detection circuit 3. The counter 9 measures the timing at which the write pulse S12 generated by the write pulse generator 8 is generated.

FIG. 6 is a flow chart for explaining the operation of the sampling timing correction circuit 4 shown in FIGS. Hereinafter, the operation of the sampling timing correction circuit 4 will be described with reference to FIG. At step 601, it is determined whether or not the edge detection signal S11 exists. If there is no signal S11, it waits for generation. When the signal S11 is detected, the process proceeds to step 602, where the signal S20 is output, and "5" is input to the counter 9. Then, the count is incremented in step 603.

Further, in step 604, the edge detection signal S
In step 605, a signal S20 is output and the counter 9 is set to "5".
Enter If there is no signal S11, it is determined in step 606 whether or not the count value of the counter 9 is "7". If it is "7", the write pulse generator 8 outputs a write pulse S12 in step 607. If the count value is not "7", the process proceeds to step 608, where the count is incremented.

As shown in the flowchart of FIG. 6, the sampling timing correction circuit 4 operates. That is, the edge detection signal S11 from the edge detection circuit 3 is input to the write pulse generator 8 of the sampling timing correction circuit 4. Upon receiving the edge detection signal S11, the write pulse generator 8 outputs an LD signal S20 to the counter 9. The counter 9 is a 3-bit counter for counting 0 to 7 in this specific example. When receiving the LD signal S20, "5" is input as the preset value of the counter 9. Thereafter, the count is incremented every clock. At the center point of the 0.5-bit signal width three clocks after receiving the LD signal S20, when the count value is “7”, which is the time when the signal level is most stable, the counter 9 sets the CY
The signal S21 is sent to the write pulse generator 8.

After that, the counter 9 similarly counts up every clock, and from "7" to "0", "1",
"2" ... and every time the count value becomes "7", CY
The signal S21 is output. The write pulse generator 8 uses CY
Each time the signal S21 is received, a write pulse S12 is generated, and the signal S12 is sent to the FIFO memory 5 to write an input signal. That is, the sampling timing correction circuit 4 outputs the edge detection signal S from the edge detection circuit 3.
When receiving 11, the write pulse S12 is generated three clocks later, and the bi-phase code signal S9 sent from the filter circuit 2 at that time is taken into the FIFO memory 5. The bi-phase code signal S9 is, as shown in FIG.
Since the signal level always changes at least once for one bit, the sampling timing is corrected at least once for one bit, and data is taken in two times for one bit.

Referring to the timing chart of FIG.
When the input data S2 in which “0” and “1” are repeated in the case of the RZ code is input, since there are two data change points in one bit, the sampling timing correction is 0.5 bit. It will be performed every time.

Therefore, even if a bi-phase code signal containing a jitter that causes a difference in signal width between the H level and the L level due to waveform distortion during transmission is input, the generation of the edge signal S11 is used as a reference. Since sampling is performed after a certain period of time, the FI
The data is taken into the FO memory 5. This indicates that the data is taken in following the timing of the change of the signal level deformed due to the temporary frequency fluctuation or jitter of the input signal S2. When outputting data, the read speed of the FIFO memory 5 is set to a constant speed determined by the read pulse S13, so that the output data S16 of the FIFO memory 5 has a constant frequency waveform from which jitter and the like have been removed. Become.

FIG. 8 is a timing chart showing the operation when the input of the jitter waveform and the input signal S 2 in which the bit rate of the input signal fluctuates are input and the data is taken into the FIFO memory 5.

FIG. 8A shows a clock signal S 1 from the clock signal generator 1. (B) is a biphase code signal input S2. (C) to (I) are signals of each unit in the filter circuit 2. (J) and (K)
Output signal S1 of D flip-flop of edge detection circuit 3
0 and the edge detection signal S11. (L) is an LD (load) signal S20 input to the counter 9 from the write pulse generator of the sampling timing correction circuit 4. (M) is a count value of the counter 9. (N) indicates that the counter 9 outputs the write pulse generator 8
Is the CY signal S21. Finally, (O) is a write pulse S12 output by the write pulse generator 8 of the sampling timing correction circuit 4.

Next, the read control circuit 6 will be described. The read control circuit 6 stores the H
When the F signal S14 is received, the read signal S13 is generated once every eight clocks. This read signal S
13, the FIFO memory 5 reads out the data fetched and stored therein in the fetching order. FIF
The O memory 5 can write and read data separately. Therefore, even if there is a difference between the speed at which data is loaded into the FIFO memory 5 and the speed at which the data is read, the FIFO
If the storage capacity of the O memory 5 is sufficient, there is time until the FIFO memory 5 becomes full (overflow) or becomes empty even if there is a speed difference (particularly a temporary speed change). The proper operation can be performed by keeping the time within the time. Also, the read control circuit 6
Generates the ENB (enable) signal S15 only once among the two generations of the read signal S13. The ENB signal S15 is sent to the code conversion circuit 7, and is used for conversion from a biphase code signal to an NRZ code signal.

Finally, the code conversion circuit 7 receives the read data S16 output from the FIFO memory 5 and the above-described ENB signal S15 from the read control circuit 6, and converts the read data S16 from the bi-phase code signal into NR signals.
The signal is converted into a Z-code signal S19. This code conversion circuit 7
It can be composed of a pair of AND gates, an inverter, and a JK flip-flop.

FIG. 9 is a timing chart for explaining the operation of the code conversion circuit 7. FIG. 9A shows the clock signal S1. (B) is a read signal S13 from the read control circuit 6. (C) is the read data S16 from the FIFO memory 5. (D)
This is the ENB signal S15 from the read control circuit 6.
(E) and (F) are output signals S17 and S18 of a pair of AND gates of the code conversion circuit 7. Also, (G)
Is the sign-converted NRZ from the JK flip-flop
This is the code signal S19.

The configuration and operation of the preferred embodiment of the demodulation circuit of the present invention have been described in detail with reference to the accompanying drawings. But,
These examples are merely examples, and those skilled in the art can easily understand that various modifications can be made without departing from the gist of the present invention.

[0040]

The demodulation circuit according to the present invention described above has the following effects. The first effect is that the demodulation side can always perform processing at a constant operation speed regardless of the state of the input biphase code signal. The reason is that the data component of the input bi-phase code signal is asynchronously fetched into the FIFO memory, so that after the data is fetched from the FIFO memory, the demodulation process can be performed using the own clock. That is, by giving the FIFO memory a buffering effect, the operation on the demodulation side can be maintained at a constant speed regardless of the state of the input signal waveform.

The second effect is that the function of shaping the waveform of the input biphase code signal can be realized. The reason is FI
The FO memory fetches only the state value (signal level) and does not include timing information such as jitter. Therefore, by making the read cycle of the FIFO memory constant, a signal waveform shaping function becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a preferred embodiment of a demodulation circuit according to the present invention.

FIG. 2 is a detailed configuration diagram of a sampling timing correction circuit of the demodulation circuit shown in FIG.

FIG. 3 is a diagram illustrating a change point (edge) of an input signal.

FIG. 4 is a timing chart for explaining the operation of the filter circuit of the demodulation circuit shown in FIG.

FIG. 5 is a timing chart illustrating the operation of the edge detection circuit of the demodulation circuit shown in FIG.

FIG. 6 is a flowchart illustrating an operation of a sampling timing correction circuit of the demodulation circuit illustrated in FIG. 1;

FIG. 7 is a waveform diagram illustrating a bi-phase code signal.

FIG. 8 is a timing chart illustrating an operation of a main part of the demodulation circuit illustrated in FIG. 1;

9 is a timing chart for explaining the operation of a FIFO memory, a read control circuit, and a code conversion circuit of the demodulation circuit shown in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Clock signal generator 2 Filter circuit 3 Edge detection circuit 4 Sampling timing correction circuit 5 FIFO memory 6 Read control circuit 7 Code conversion circuit 8 Write pulse generator 9 Counter

Claims (8)

[Claims] An edge detection circuit for detecting a change point of an input signal level; a sampling timing correction circuit for correcting a sampling timing of the input signal based on an edge detection signal of the edge detection circuit; A FIFO memory for storing the input signal based on a write pulse and reading the input signal at a constant period. 2. The demodulation circuit according to claim 1, wherein a noise filter for removing noise of the input signal is provided at a stage preceding the edge detection circuit. 3. The demodulation circuit according to claim 1, wherein the input signal is a bi-phase code signal. 4. The method according to claim 1, wherein the read data of said FIFO memory is N
The demodulation circuit according to claim 3, further comprising a code conversion circuit that converts the signal into an RZ code signal. 5. The demodulation circuit according to claim 2, wherein said filter circuit comprises a plurality of cascade-connected D flip-flops, AND gates, inverters, and JK flip-flops. 6. The demodulation circuit according to claim 1, wherein said edge detection circuit comprises a D flip-flop and an EX-OR gate. 7. The sampling timing correction circuit according to claim 1,
7. The demodulation circuit according to claim 1, comprising a write pulse generator and a counter. 8. A clock signal generator, a filter circuit for removing noise of an input signal, an edge detection circuit for detecting an edge of an output signal of the filter circuit, and a timing according to an edge detection signal of the edge detection circuit. A sampling timing correction circuit for correcting, a FIFO memory for taking in output data of the filter circuit with an output of the sampling timing correction circuit, and a readout for periodically reading data stored in the FIFO memory by a clock signal of the clock signal generator A demodulation circuit comprising a control circuit.