JPH0410776B2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field) The present invention implements a circuit using a digital circuit that sequentially calculates the average value of values over a certain period of time and detects whether the average value exceeds a preset value. It is for the purpose of

(Background Art) FIG. 1 shows an example of a conventional delay detection circuit partially digitized. 1 is the input terminal, MSK
A digital phase modulated signal such as (Minimum Shift Keying) is added. A delay circuit 2 provides a delay corresponding to, for example, one bit of the digital signal. 3 is an exclusive OR circuit,
Reference numeral 4 denotes a low-pass filter, which is used to give the output of the exclusive OR circuit 3 an average value for approximately one bit of the digital signal. Show the diagram. 5 is an analog comparator, and the output of the low frequency converter 4 is
It determines whether the voltage of digital "1" exceeds, for example, 1/2. If it exceeds 1/2, it outputs "1", and if it does not exceed,
Outputs "0". An example of the analog comparator 5 is an operational amplifier as shown in FIG.

FIG. 4 shows an example of the output waveform of each part in FIG. 1, and the horizontal axis is the time axis. Figure 4
EXOR is the output of the exclusive OR circuit 3, and is set to “1” by the digital signal input from the input terminal 1.
The width of "0" changes. The LPF shown in FIG. 4 is the output of the low frequency filter 4, and time averaging of approximately one bit of the digital signal is performed. The dotted line parallel to the horizontal axis is
"1" and "0" indicate 1/2 of the output, and with this level as the border, the output of analog comparator 5 is the fourth
Changes as shown in COMP in the figure.

By the way, since the low frequency converter 4 and analog comparator 5 in FIG. 1 are analog circuits,
The drawback was that it was extremely difficult to convert into an LSI.

(Object of the Invention) An object of the present invention is to provide a moving average value detection method suitable for LSI implementation.

(Summary of the Invention) The configuration of the present invention includes a sampling clock oscillator, an M+1 (M is a positive integer) stage shift register that is written in synchronization with the clock oscillator, an up-down counter that can count up to at least M, and A digital comparator is provided, and if the data in the first stage of the shift register and the M+1 stage where data is written last are the same value, it is not counted, and the data in the first stage and the M+1 stage of the shift register are different. In this case, the up-counting or down-counting is performed in synchronization with the clock oscillator depending on the different state, and in addition, when the count number of the up-down counter reaches "M", the up-counting condition is satisfied. This moving average value detection method is characterized in that it does not count up even if the count of the up-down counter reaches "0", and it does not count down even if the conditions for counting down are met. Examples will be described in detail below.

(Structure and operation of the invention) FIG. 5 is a circuit for explaining the first embodiment of the present invention, 1, 2, 3, and 6 are the same as those in FIG. 1, and 7 is M+1 8 is a sampling clock oscillator, and 9 is a logic circuit. Input the M+1st row. 10 is an up-down counter that can count up to at least M, and 11 is a digital comparator. The output data of the exclusive OR circuit 3 is sampled according to the clock of the sampling clock oscillator 8 and read into the first stage A of the M+1 stage shift register 7. This read data is shifted to the right every time the clock of the sampling clock oscillator 8 advances one cycle, and the sampling data read into the first stage A is processed by M sampling clocks.
It is shifted to the M+1 stage B of the M+1 stage shift register 7.

The logic circuit 9 performs a logical operation as shown in FIG. 6, and controls the up-count and down-count of the up-down counter 10 according to the contents of the first stage A and the M+1 stage B of the M+1 stage shift register 7. Determine the count.

The frequency fc of the sampling oscillator 8 is a high frequency that samples the output from the exclusive OR circuit 3 as faithfully as possible, and is generally more than twice the highest frequency that needs to be reproduced according to Shannon's theorem. There is one condition. Furthermore, a frequency determined by the following calculation formula is selected.

fc=M/T where T is the length of time for obtaining the average value.

Next, the operation of the circuit configured as described above will be explained.

First, it is assumed that the contents of each stage of the shift register 7 and the contents of each bit of the up-down counter are all "0". When the sampling clock 8 advances by one cycle, the sampling data is first taken into the first stage A of the shift register 7. Assuming that this value is "1", the value of A moves to the second stage of the shift register 7 at the next sampling clock, and from the logic operation shown in FIG. do. Thereafter, the sampling data is sequentially moved within the shift register 7 in accordance with the sampling clock, and the contents of the up-down counter 10 are increased by the number of "1"s in the sampling data. When the number of sampling clocks reaches M, the first sampling data appears in the M+1 stage B of the shift register 7, and the number whose content is "1" in each stage from the 2nd stage to the M+1 stage is the content of the up-down counter 10. matches. Next, the first stage A and M+ of the shift register 7
When the values in the first stage match, the number of "1"s in the second to M+1 stages does not change even if the contents of the shift register are shifted one stage at a time at the next sampling clock. At this time, the contents of the up-down counter 10 do not change either. Furthermore, when the content of the first stage A of the shift register 7 is "1" and the content of the M+1st stage B is "0", the next sampling clock
The number of "1"s in the M+1th row increases by one, and the contents of the up-down counter 10 also increase by one.
Conversely, the content of the first stage A of shift register 7 is "0"
So, when the content of the M+1st stage is "1", the number of "1"s in the 2nd stage to the M+1st stage of the shift register 7 is 1.
The content of up-down counter 10 also decreases by 1.
decrease by one.

As can be understood from the above explanation, the number of "1"s in the second to M+1 stages of the shift register 7 and the contents of the up-down counter 10 always match. Therefore, digital comparator 1
By comparing the value with the value set in advance at 1, an output indicating whether the value has been exceeded can be obtained at the output terminal 6. In addition, the second stage ~M of the shift register 7
The number of "1"s in the contents of the +1st row is T from that time.
It shows how often the number ``1'' has occurred up to the time that has gone back in time, and if this number is compared with M, it means that the time average within the above time period has been calculated. Since the contents of the shift register 7 change sequentially in accordance with the period of the sampling oscillator 8, a moving average value within time T is obtained.

To detect whether the average value exceeds 1/2, M/2 may be set in the digital comparator 11. When detecting whether the average value exceeds an arbitrary value between 0 and 1, the digital comparator 11 multiplies the arbitrary value between 0 and 1 by M.
You can set it to .

By the way, in the first embodiment shown in FIG.
“1” in the 2nd to M+1st stages of the shift register 7
If the number of up-down counters 10 and the contents of the up-down counter 10 do not match for some reason (disturbances such as noise), a problem arises in that the correct average value is not detected.

The second embodiment is improved to prevent this, and is shown in FIG. 12,1 in Figure 7
3 is a logic circuit, and other symbols are the same as in FIG. When the content of the up-down counter 10 reaches M, the logic circuit 12 closes the gate of the logic circuit 13 to which the output of the logic circuit 9 is input.
Even if an up-count instruction is issued from the logic circuit 9, it will not be counted; conversely, if the content of the up-down counter 10 is 0, the gate of the logic circuit 13 will be closed even if a down-count instruction is issued from the logic circuit 9. , prevent it from being counted.

Next, to explain the operation of FIG. 7, if for some reason the value of the up-down counter 10 becomes larger than the contents of the shift register 7, when the sampling data becomes a series of "1",
Before the contents of the shift register 7 become all "1", the contents of the up-down counter 10 become M. However, because the logic circuits 12 and 13 do not count up any more, if the number of 1's starts to decrease after all the values in the shift register 7 become "1", the shift register 7
The number of "1"s in the second to M+1 rows and the value of the up-down counter 10 come to match.

Similarly, when the value of the up-down counter 10 becomes smaller than the contents of the shift register 7, it is corrected when the values of the second stage to M+1 stage of the shift register 7 all become "0". Thereafter, the contents of the shift register 7 and the contents of the up-down counter 10 will match.

There is an extremely high probability that the sampling data will be all "1" or all "0" for T time, so in rare cases the contents of the shift register 7 and the contents of the up-down counter 10 will not match. The correct average value can always be detected.

Note that, as illustrated as the third embodiment in FIG.
By adding 4 and giving a hysteresis characteristic to the detection operation of the digital comparator 11, the operation can be made more stable. That is, for example, when the output of the digital comparator 11 is "0", the detection point level when it becomes "1" next time is raised by a certain value (for example, raised by 2), and conversely, the output of the digital comparator 11 is "0". If the detection point level of the digital comparator 11 is lowered by a certain value (for example, lowered by 2) the next time it becomes "1" when it is "0", the output can be raised or lowered in a short time due to small fluctuations in the input signal. Since there is no need to do this, stable operation can be achieved. This can be applied to both the first embodiment shown in FIG. 5 and the second embodiment shown in FIG. This is effective when handling signals with a lot of noise.

(Effects of the Invention) As described above, in the first, second, and third embodiments, up-counting is performed when the data in the first stage of the shift register 7 is "1" and the data in the M+1 stage is "0". It was something I made. By connecting the inverter 15 after the comparator 11 as shown in FIG. 9, it is easy to down-count when the data in the first stage of the shift register 7 is "1" and the data in the M+1 stage is "0". When the data in the first stage of the shift register 7 is "0" and the data in the M+1 stage is "1", a moving average value detection method can be realized by up-counting.

As explained above, since the moving average value can be detected by configuring a simple digital circuit, LSI implementation is possible.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional configuration, Figure 2 is an example of a circuit diagram of a conventional low frequency converter, Figure 3 is an example of a circuit diagram of a conventional analog comparator, and Figure 4 is an example of the circuit diagram of a conventional analog comparator. Waveform diagrams of various parts, FIG. 5 is a circuit diagram showing one embodiment of the present invention, FIG. 6 is a diagram showing the operation of the logic circuit 9, FIG. 7 is a circuit diagram showing a second embodiment of the present invention, FIGS. 8 and 9 are circuit diagrams for explaining third and fourth embodiments of the present invention. 1... Input terminal, 2... Delay circuit, 3... Exclusive OR circuit, 6... Output terminal, 7... Shift register, 8... Sampling clock oscillator,
9...Logic circuit, 10...Up-down counter, 11...Comparator, 12, 13, 14...
...Logic circuit, 15...Inverter.

Claims (1)

[Scope of Claims] 1. A sampling clock oscillator, an M+1 (M is a positive integer) stage shift register written in synchronization with the clock oscillator, and at least:
It is equipped with an up-down counter that can count up to M, and a digital comparator.If the data in the first stage of the shift register and the M+1 stage, where data is written last, are the same value, no counting is performed and the first stage of the shift register is A moving average value detection method characterized in that when the data at the 1st stage and the M+1th stage are different, up-counting or down-counting is performed in synchronization with the clock oscillator depending on the different state. 2 When the data in the first stage of the shift register is "1" and the data in the M+1 stage is "0", it counts up or down, and the data in the first stage of the shift register becomes "0". The moving average value detection method according to claim 1, characterized in that when the data in the M+1st row is in a different state of "1" in "1", down-counting or up-counting is performed. 3. A sampling clock oscillator, an M+1 (M is a positive integer) stage shift register written in synchronization with the clock oscillator, an up-down counter capable of counting up to at least M, and a digital comparator, the first stage of the shift register If the data in the M+1st stage and the M+1st stage, where data is finally written, are the same value, it is not counted, and if the data in the 1st stage of the shift register and the M+1st stage are different, the above-mentioned values are counted according to the different states. Up-counting or down-counting is performed in synchronization with the clock oscillator, and when the count number of the up-down counter is M, even if the up-counting conditions are met, the up-counting does not occur, and the up-down counter does not count. Number,
A moving average value detection method characterized in that when the value becomes 0, the down-count is not performed even if the down-counting conditions are satisfied.