JP3826530B2 - Bit synchronization circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bit synchronization circuit that generates a bit synchronization pulse used in, for example, a paging receiver.
[0002]
[Prior art]
In the paging receiver, the received FSK (Frequency Shift Keying) signal is converted into a binary signal of NRZ (Non Return to Zero), and the level of the binary signal is high or low. Is converted into digital data.
[0003]
In order to perform the conversion to digital data, that is, the data demodulation accurately, it is desirable that the level determination of the demodulated signal is performed near the center of each bit period. A bit synchronization circuit for synchronization is provided. Conventionally, a bit synchronization circuit for generating a bit synchronization pulse has a configuration as shown in FIG.
[0004]
In the figure, an input signal (for example, NRZ signal) is first input to the edge detector 11, where an edge pulse corresponding to the edge position of the signal waveform is output as a detection signal and sent to the edge number counter 13.
[0005]
The edge number counter 12 counts the number of edges entered in one frame corresponding to one data bit length of the input signal by the edge pulse from the edge detector 11, and increases or decreases the count value (number of edges). Output to.
[0006]
The edge number counter 12 is integrated into an LSI with an addition accumulator 15 composed of an adder and a register. The addition accumulator 15 accumulates and holds a count value of an up / down counter 17 described later. Then, the stored cumulative value is output to the increase / decrease determination circuit 14.
[0007]
The edge number counter 13 is the same as the edge number counter 12, and counts the number of edges that enter one frame corresponding to one data bit length of the input signal by the edge pulse from the edge detector 11, and the count value ( The number of edges) is output to the increase / decrease determination circuit 14.
[0008]
The edge number counter 13 is integrated into an LSI together with an adder accumulator 16 that is also composed of an adder and a register. The adder accumulator 16 accumulates the count value of an up / down counter 17 described later. The accumulated value held is output to the increase / decrease determination circuit 14.
[0009]
The increase / decrease determination circuit 14 determines a bit synchronization shift based on the number of edges from the edge number counter 12 and the accumulated value from the adder accumulator 15, the number of edges from the edge number counter 13 and the accumulated value from the adder accumulator 16. Then, an up signal or a down signal corresponding to the determination result is sent to the up / down counter 17.
[0010]
The up / down counter 17 is, for example, further in accordance with an up / down signal from the increase / decrease determination circuit 14 with respect to a normal count operation that counts up one by one with a clock of an integer multiple (for example, 16 times) of the bit rate of the input signal An up-counting operation for counting up by 1 and a down-counting operation for removing the count-up operation once are executed.
[0011]
However, the count value of the up / down counter 17 is sent to the adder accumulators 15 and 16 as described above, and the half carry signal (HCY) output when the count value reaches half of the full count value (for example, 16). ) Is supplied to the increase / decrease determination circuit 14 as a reset signal and as a clear signal to the adder / accumulator 16, and is used as a synchronization pulse signal in a data demodulator circuit (not shown) and other internal circuits (not shown). A half carry signal and a full carry signal (FCY) output when the count value reaches the full count value are supplied as a reset signal to the increase / decrease determination circuit 14 and a clear signal to the adder / accumulator 15, respectively. Used in the circuit.
[0012]
Reference numeral 18 denotes a bus control unit for controlling the signal buses of the circuits 11 to 17.
[0013]
[Problems to be solved by the invention]
In the circuit configuration as described above, since the edge number counters 12 and 13 and the adder accumulators 15 and 16 are particularly required, the scale of the entire circuit increases as a result, and the up / down counter 17 Since the operation is performed only by the up / down signal from the increase / decrease determination circuit 14, the pull-in operation is slow, the synchronous convergence operation is slow, and the degree of freedom in circuit design is low.
[0014]
The present invention has been made in view of the above circumstances, and its purpose is to reduce the circuit scale as much as possible, while achieving a fast synchronous convergence operation, high stability, and flexibility in the circuit. It is an object of the present invention to provide a bit synchronization circuit capable of improving the above.
[0015]
[Means for Solving the Problems]
According to the first aspect of the present invention, an edge detecting means for detecting an edge position of an input binary signal and an N for counting a clock having a frequency N times (N = 2, 3,...) Of the binary signal. Obtained by subtracting the holding value of the holding means from the count value of the counter, the holding means for holding the input value given at the edge position detected by the edge detecting means as the holding value, a difference output, at the time of convergence, said difference output is sawtooth shaped signal, the difference output timing difference output becomes "0" is a timing synchronized with the edge timing of the binary signal A subtracting means for outputting as a synchronizing signal of the binary signal, a limiting means for limiting the difference output of the subtracting means at a fixed rate, an output of the limiting means and a holding value of the holding means are added, and the sum A force, characterized by comprising an adding means for providing as the input value to said holding means.
[0016]
With such a configuration, the circuit scale is reduced and the power consumption is reduced, while the synchronous convergence operation is fast and stable, and it is easy by changing the limiting characteristics of the limiting means provided independently. Convergence characteristics can be selected, and the degree of freedom of the circuit can be improved because the configuration of the circuit portion that operates by receiving the clock signal directly is small.
[0017]
According to a second aspect of the present invention, in the first aspect of the invention, the waveform obtained by shaping the difference output as the synchronizing signal output from the subtracting means to obtain a signal synchronized with a desired sampling position of the binary signal. It further comprises shaping means.
[0018]
With such a configuration, in addition to the operation of the first aspect of the invention, it is possible to obtain a signal that is more accurately synchronized with the input binary signal.
[0019]
According to a third aspect of the present invention, in the first aspect of the present invention, the holding value of the holding unit is supplied to the adding unit and the subtraction is performed to the limiting unit depending on whether the edge position is detected by the edge detecting unit. The apparatus further comprises gate control means for controlling supply of the differential output of the means.
[0020]
With such a configuration, in addition to the operation of the first aspect of the invention, the power consumption can be further reduced.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment in which the present invention is applied to a bit synchronization circuit used in a receiving circuit of a paging receiver will be described below with reference to the drawings.
[0022]
FIG. 1 shows the circuit configuration. An input signal, that is, an NRZ signal obtained from a received FSK signal is first input to an edge detector 21 where a pulse corresponding to the edge position of the signal waveform is generated as a detection signal. And sent to the n + m bit register 22.
[0023]
The n + m bit register 22 holds the sum output f of (n + m) bits sent from an adder 23, which will be described later in detail, using the edge pulse a from the edge detector 21 as a latch pulse, and again holds the held content b. The adder 23 and the upper n bits thereof are sent to the subtractor 24, respectively.
[0024]
Further, 25 in the figure has a frequency N times (“N = 2, 3,...” And “N ≦ 2 ⁿ (n = 1, 2,...)”) Of the NRZ signal given from the outside. This is an N-ary free-run counter that counts the clock, and its n-bit count value c is sent to the subtractor 24.
[0025]
The subtractor 24 subtracts the count value c from the free-run counter 25 by subtracting the upper n bits of the content b held in the n + m bit register 22 as a subtraction, and outputs the difference output d of (n + 1) bits to the limiter 26 and the output waveform. Send to generator 27.
[0026]
The limiter 26 limits the difference output d taking the range of “− (N / 2)” to “+ (N / 2) −1” from the subtractor 24 to p bits, and the limit range is ± α (2α ≦ 2 ^p ), and the limited p-bit difference output signal e is sent to the adder 23.
[0027]
The adder 23 adds the (n + m) -bit held content b from the n + m-bit register 22 and the p-bit difference output signal e limited through the limiter 26, and removes the most significant carry (n + m). The bit sum output f is sent to the n + m bit register 22 and held as described above.
[0028]
Thus, the output waveform generator 27 shapes the difference output d from the subtractor 24 to generate and output a bit synchronization pulse that is accurately synchronized with the position in the bit period of the input signal.
[0029]
In the circuit configuration as described above, when there is no signal input, or when there is no change in the level even if there is a signal input, the edge pulse a from the edge detector 21 is not input, so the n + m bit register The held content b of 22 does not change. Therefore, the output waveform generator 27 shapes the difference output d output from the subtractor 24, that is, the value obtained by subtracting the upper n bits of the retained content b of the n + m bit register 22 from the count value c of the free-run counter 25. Is output as a bit synchronization pulse.
[0030]
When a signal is input and an edge pulse a is output from the edge detector 21 to the n + m bit register 22 due to a change in the level, the n + m bit register 22 outputs the sum of the adder 23 for each input of the edge pulse a. Since f is latched and output as held content b, the value gradually converges following the position of the edge with respect to the value of the free-run counter 25.
[0031]
FIGS. 2A and 2B both illustrate the relationship between the edge position with respect to the count value of the free-run counter 25 indicated by a circle and the held value of the n + m bit register 22. The position of the edge with respect to the count value of the free-run counter 25 is shown, and the white circle indicates the value held in the register 22.
[0032]
As shown in the figure, the value held in the register 22 converges following the position of the edge with respect to the count value of the free-run counter 25. Here, the limiter 26 is set to 1 for the difference output d of the subtractor 24 as an input value. The case where the operation is performed with a / 2 circuit is shown, and the convergence is the same as the operation using the first-order filter.
[0033]
However, mathematically verifying the state of convergence is as follows.
[0034]
In other words, when the initial value of the phase shift between the value held in the register 22 and the position of the edge with respect to the value of the free-run counter 25 is δ, every time an edge is detected, the next calculation δ ′ = f (q (1)
(However, f (q): Limiter function.)
To do. In the above example, since the limiter 26 is a 1/2 circuit, the limiter function f (x) = x / 2 (2)
It is.
[0035]
From the above formulas (1) and (2), δ ′ = (δ) / 2 (3)
If the input t of the edge pulse a is a parameter,
δ (t) = δ ₀ · (1/2) ^t (4)
(However, δ _{0 is} the initial value of the phase difference.)
It becomes. From this equation (4), it can be seen that the configuration shown in FIG. 1 operates as a primary filter.
[0036]
In general, convergence with respect to a limiter circuit using a 1 / k circuit (1 <k) is expressed by the following equation δ (t) = δ ₀ · (1− (1 / k)) ^t (5)
When a constant (± γ) is selected as the limiter, convergence is δ ′ = δ−γ, or δ ′ = δ + γ (6)
It becomes. Here, using the parameter t,
δ (t) = δ ₀ −γ · t, or δ (t) = δ ₀ + γ · t
And can be expressed by a linear expression.
[0037]
With the above operation, after the circuit system has converged, the difference output d of the subtractor 24 is always “0 (zero)” when the edge pulse a is input, and the value of the content b held in the n + m bit register 22 does not change.
[0038]
With such a configuration, instead of the up / down counter 17 shown in FIG. 4, a free-run counter 25 that simply performs a cyclic counting operation using a clock signal is used, and other configurations are also shown in FIG. As compared with the above, the circuit scale is greatly reduced and the power consumption is reduced, and the synchronous convergence operation is fast and the stability can be improved.
[0039]
Further, the convergence characteristic can be easily selected by providing the limiter 26 independently and changing the limiting characteristic.
[0040]
Note that the limiter 26 limits the difference output d of the subtractor 24 with a constant as described in the case where the limiter 26 is realized with, for example, a 1/2 circuit. Alternatively, various configuration examples such as a table pickup type using a memory can be considered.
[0041]
When the NRZ signal, which is an input signal, is not input to the edge detector 21, the contents b stored in the n + m bit register 22 to the adder 23 and the difference output d from the subtractor 24 to the limiter 26 are supplied. By temporarily disconnecting, it is possible to reduce the gate operation rate of the entire circuit and reduce wasteful power consumption.
[0042]
FIG. 3 exemplifies another circuit configuration of the embodiment of the present invention, and is basically the same as that shown in FIG. The description thereof will be omitted.
[0043]
Thus, the edge detector 21 'that generates the edge pulse a corresponding to the edge position of the signal waveform of the input signal as a detection signal has the edge position a synchronized with the center position of the pulse and has a sufficient pulse width. A large gate pulse x is generated separately, and the generated gate pulse x is sent to the gate circuits 31 and 32, respectively.
[0044]
The gate circuit 31 cuts off the stored content b of the n + m bit register 22 supplied to the adder 23 when there is no input of the gate pulse x from the edge detector 21 '.
[0045]
Similarly, the gate circuit 32 cuts off the difference output d of the subtractor 24 supplied to the limiter 26 when there is no input of the gate pulse x from the edge detector 21 '.
[0046]
As described above, when the edge detector 21 'cannot detect an edge from the input signal, that is, when there is no signal input or when there is no signal input, the level of the adder 23 does not change. Further, the gate operation rate in each circuit is reduced by cutting off the input to the limiter 26. As a result, the gate operation rate in the entire circuit can be lowered, and the power consumption can be further reduced.
[0047]
In the above embodiment, the bit synchronization circuit used in the receiving circuit of the paging receiver has been described. However, the present invention is not limited to this, and any circuit that generates bit synchronization pulses by synchronizing with the input signal can be used. Needless to say, other applications are possible.
[0048]
In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.
[0049]
【The invention's effect】
According to the first aspect of the invention, the circuit scale is reduced and the power consumption is reduced, and the synchronous convergence operation is fast, the stability is high, and the limiting characteristic of the limiting means provided independently is changed. Convergence characteristics can be easily selected, and the degree of freedom of the circuit can be improved because the number of circuit units that operate by receiving a clock signal is small.
[0050]
According to the second aspect of the invention, in addition to the effect of the first aspect of the invention, it is possible to obtain a signal more accurately synchronized with the input binary signal.
[0051]
According to the invention described in claim 3, in addition to the effect of the invention described in claim 1, the power consumption can be further reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining an operation according to the embodiment;
FIG. 3 is a block diagram showing another circuit configuration according to the embodiment;
FIG. 4 is a block diagram showing a configuration of a conventional bit synchronization circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Edge detector 12, 13 ... Edge number counter 14 ... Increase / decrease determination circuit 15, 16 ... Addition accumulator 17 ... Up / down counter 18 ... Bus control part 21,21 '... Edge detector 22 ... n + m bit register 23 ... Addition 24: Subtractor 25 ... Free-run counter 26 ... Limiter 27 ... Output waveform generator 31, 32 ... Gate circuit

Claims (3)

Edge detection means for detecting the edge position of the input binary signal;
An N-ary counter for counting clocks having a frequency N times (N = 2, 3,...) Times the binary signal;
Holding means for holding an input value given at the edge position detected by the edge detecting means as a holding value ;
The difference output obtained by subtracting the holding value of the holding means from the count value of the counter, and at the time of convergence, the difference output is a sawtooth signal, and the timing when the difference output becomes “0” There subtracting means and outputting the difference output is a timing synchronized with the edge timing of the binary signal as a synchronizing signal of said binary signal,
Limiting means for limiting the difference output of the subtracting means at a fixed rate;
A bit synchronizing circuit comprising: an adding means for adding the output of the limiting means and the holding value of the holding means and giving the sum output to the holding means as the input value . 2. The bit according to claim 1, further comprising waveform shaping means for obtaining a signal synchronized with a desired sampling position of the binary signal by shaping the difference output as a synchronizing signal output from the subtracting means. Synchronous circuit. Gate control means is further provided for controlling the supply of the holding value of the holding means to the adding means and the supply of the difference output of the subtracting means to the limiting means depending on whether or not the edge position is detected by the edge detecting means. The bit synchronization circuit according to claim 1.

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