JPH04324709A - Noise elimination circuit - Google Patents

Abstract

PURPOSE:To eliminate noise in an input signal by varying a count between reference values when noise is invaded while the count of an up-down counter is converged into a 1st reference value or a 2nd reference value. CONSTITUTION:When a signal of an H level is inputted to a terminal 30 for a prescribed period, the count of an up-down counter 10 goes to H or L and it is given to a logic circuit 20. An output of an L level of the circuit 20 in this case is given to one terminal of the logic circuit 40. When a noise invades in an input signal at the terminal 30 and the level changes from H to L, the circuit 40 outputs a signal of an L level, the count is being decremented while the noise takes place thereby keeping an output at a terminal 60 to be an H level at all times. Then the input signal at the terminal 30 changes to an H level, the count is incremented and the circuit reaches the stable state. Furthermore, the similar operation as to noise of the input signal of an L level at the terminal 30 is implemented as above.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise removal circuit that removes noise by majority voting when a digital signal contains noise.

0002

[Prior Art] Conventional noise removal circuits of this type include:
A large number of flip-flop circuits 2 as shown in FIG.
Those using numbers 01 to 203 are known. The outputs from each of the flip-flop circuits 201 to 203 are given to a majority circuit 210, and noise components are removed by majority logic processing.

0003

[Problems to be Solved by the Invention] However, such conventional noise removal circuits require a large number of flip-flop circuits in order to improve the accuracy of noise removal, and also require input signals from these flip-flop circuits. In order to do this, a majority voting circuit with a large number of input terminals was required. Therefore, there was a problem that the circuit configuration became large-scale.

An object of the present invention is to solve these problems and simplify the circuit configuration.

[0005]

[Means for Solving the Problems] In order to solve the above problems, the noise removal circuit of the present invention increases a count value when a first level signal is applied, and a second level signal is applied. and an up-down counter that decreases a count value, and an input signal and a signal indicating the count value of the up-down counter, and when the count value of the up-down counter is equal to or higher than a predetermined first reference value or lower than the first reference value, A count control circuit is provided that inverts the input signal and supplies it to the up-down counter when the input signal is equal to or less than a small predetermined second reference value, and the count control circuit inverts the input signal and supplies it to the up-down counter when the count value of the up-down counter is between the first reference value and the second reference value. A first level signal is output when the value is closer to the first reference value than the arbitrary value selected in , and a second level signal is output when the value is closer to the second reference value.

[0006]

[Operation] Since the noise removal circuit of the present invention is constructed as described above, while the count value of the up/down counter is smaller than the predetermined first reference value, the first level input signal applied to the count control circuit is It is input directly to the up/down counter. Here, when the first level input signal is input continuously, the up/down counter
The level signal continues to be input, and the count value increases. When the count value reaches the first reference value, the first level input signal is inverted by the count control circuit, and the second level signal is input to the up/down counter. This input causes the count value of the up-down counter to decrease by one, and the signal applied from the count control circuit to the up-down counter returns to the first level signal. In this way, when the first level signal is continuously input, the count value converges to the first reference value.

Similarly, when second level input signals are continuously input, the count value converges to the second reference value.

[0008] In this way, if noise enters in a state where the count value of the up/down counter has converged to the first reference value or the second reference value, the count value becomes an arbitrary value between the first reference value and the second reference value. Change the value in the direction closer to . However, since the output signal maintains a constant value unless the count value exceeds an arbitrary value, noise contained in the input signal can be removed.

[0009]

[Example] Hereinafter, with reference to FIGS. 1 to 3 of the accompanying drawings,
An embodiment of the present invention will be described.

FIG. 1 is a block diagram of a noise removal circuit according to an embodiment of the present invention. The noise removal circuit of this embodiment includes an up/down counter 10 that performs majority voting processing, a logic circuit 20 that takes the negative exclusive OR of the upper two digit output signals of the up/down counter 10, and an output signal of the logic circuit 20. A logic circuit 40 receives a digital input signal from an input terminal 30, calculates an exclusive OR, and supplies the result to an up/down counter 10. The up/down counter 10 is
The signal value of the input signal is counted by the clock signal applied from the clock terminal 50, and the most significant bit of the output signal output in parallel is outputted from the output terminal 60.

Next, the operation of this noise removal circuit will be explained. The input signal applied to the input terminal 30 is a digital signal having two levels: high level and low level. The logic circuit 40 calculates the exclusive OR of this input signal and the signal from the logic circuit 20. That is, when the signal from the logic circuit 20 is a high level signal, an inverted signal of the input signal is output from the logic circuit 40, and the logic circuit 20
If the signal from 0 is a low level signal, the input signal is output from the logic circuit 40 as it is. The signal outputted from the logic circuit 40 in this manner is given to the up/down counter 10 as an input signal. In the up/down counter 10, when the input signal is a high level signal, one is added to the count value, and when the input signal is a low level signal, the count value is subtracted by one. This up/down counter 10 counts 2N+1 and outputs this count value from output terminals Q0 to QN. Then, the output from the output terminal QN is given to the output terminal 60 as the output of the entire circuit. Further, signals from output terminals QN and QN-1 are given as input signals to the logic circuit 20. In the logic circuit 20, a high level signal is given to the logic circuit 40 when the two input signals are both high level and when both are low level, and a low level signal is given when the two input signals are high level and low level. A signal is provided to logic circuit 40.

Next, the operation of the up/down counter 10 will be explained. First, the count value of the up/down counter 10 is "LLLL...LLLL" (L represents a low level binary number), and the input terminal 30 is When the input signal applied to the logic circuit 20 is a signal that maintains a high level state for a certain period of time, a low level input signal is applied to the logic circuit 20. Therefore, the output signal from the logic circuit 20 becomes high level, and the signals applied to the logic circuit 40 both become high level signals. Since the logic circuit 40 performs exclusive OR, the output signal from the logic circuit 40 becomes a low level signal. This low level signal is applied to the up/down counter 10, and the count value is subtracted by one. In other words, the count value becomes "HHHH...HHHH" (H represents a high-level binary number), and the output signal from the output terminal 60 becomes a high-level signal. logic circuit 20
The input signals applied to both change to high level signals, but since the negative exclusive OR is taken, the output signals remain high level signals. Therefore, input terminal 30
As long as the input signal provided from the logic circuit is at a high level, the output from the logic circuit maintains a low level signal. Therefore, the next clock pulse is the up/down counter 10
, the count value is decremented by one. However, since the most significant digit of the count value remains at a high level, a high level signal is output from the output terminal 60. In this way, the upper two digits of the count value are "HH", and the input terminal 3
While the input signal to 0 is at a high level, the count value of the up/down counter 10 is decremented by one each time a clock pulse is applied. This state continues until the count value reaches "HLHH...HHHH".
The output signal applied to the output terminal 60 is maintained at a high level. Then, the count value is “HLHH…H
HHH'', the input to the logic circuit 20 changes to high level and low level signals, and the output signal also changes from high level to low level. Therefore, the high-level signal from the input terminal 30 and the low-level signal that is the output signal of the logic circuit 20 become input signals to the logic circuit 40, exclusive OR is taken, and the logic circuit 40 outputs a high-level signal. A level signal is output. Then, when the next clock pulse is applied, the count value of the up/down counter 10 is incremented by one and becomes "HHLL...LLLL". In this count value, the top two digits of the count value are also “
HH", the count value of the up/down counter 10 is decremented by one at the next clock signal. Therefore, if a high level signal is continuously applied from the input terminal 30, the count value of the up/down counter 10 will be "H".
It will now indicate either "LHH...HHHH" or "HHLL...LLLL".

Furthermore, when the input signal applied to the input terminal 30 is a signal that maintains a low level state for a certain period of time, the count value of the up/down counter 10 changes as "LHLL...LLLL" every clock. “LLH
H...HHHH".

As described above, when a high level or low level input signal is applied to the input terminal 30 for a certain period of time and the count value of the up/down counter 10 indicates one of two values, the maximum count value The upper digits are signals at the same level as the input signal applied to the input terminal 30. Therefore, the output signal applied to the output terminal 60 is at the same level as the input signal.

Next, noise removal, which is a feature of this embodiment, will be explained. As an example, the operation of this circuit will be described when low level noise is input for 6 clocks while a high level signal is being applied to the input terminal 30 for a certain period of time. As described above, when a high-level signal is applied to the input terminal 30 for a certain period of time, the count values of the up/down counter 10 become "HLHH...HHHH" and "HHLL...
LLLL”. The count value is “HLH”
H...HHHH'', the logic circuit 20 is given high-level and low-level signals, which are the upper two digits of the count value. In the logic circuit 20, the negative exclusive OR of these signals is taken, so a low level signal is output. Therefore, one of the input signals to the logic circuit 40 becomes a low level signal. In this state, when noise enters the input signal from the input terminal 30 and changes from a high level to a low level signal, the other input signal to the logic circuit 40 becomes a low level signal. Since the logic circuit 40 performs exclusive OR, a low level signal is output. Since this low level signal is given to the up/down counter 10, the count value is subtracted by one to "HLHH...HHHL" by the clock pulse. Since the upper two digits of the count value remain "HL", the output of the logic circuit 20 is also a low level signal. The output of the logic circuit 40 to which this low level signal is applied is also a low level signal. Therefore, the count value of the up/down counter 10 continues to be subtracted during the 6 clocks during which noise occurs, so the count value after 6 clocks is "HLHH...HLLH". Even at this stage, the most significant digit of the count value is at a high level. In other words, during 6 clocks when the input signal contains noise, the output terminal 60
The output signal given to the is always a high level signal. After that, the input signal applied from the input terminal 30 changes to a high level signal, and the count value of the up/down counter 10 is added up, and the stable state is reached.
Recovers to HLHH...HHHH. In this example, 6
Although we simulated clock noise, this circuit can remove noise even longer than this. Specifically, since it is sufficient that the most significant digit of the count value is at a high level, a high level output signal can be held until the count reaches "HLL...LLLL". In other words, noise with a length of 2N-1 clocks can be removed. The same applies to noise to low-level input signals.

Next, the embodiment shown in FIG. 2 will be explained. FIG. 2 shows an embodiment of the present invention using a four-digit up/down counter 110. In this circuit, an input signal from an input terminal 120 is applied to a logic circuit 140 via an inversion circuit 130. This logic circuit 140 performs an exclusive OR, and the result is given to the up/down counter 110 as an output signal. Up-down counter 110 operates in exactly the opposite way to up-down counter 10 used in the embodiment of FIG. That is, when the applied signal is a low level signal, the count value is added by one, and when the applied signal is a high level signal, the count value is subtracted by one. Then, the output signal from the output terminal Q3 of the up/down counter 110 is applied to the output terminal 150. Further, output signals from output terminals Q2 and Q3 are applied to a logic circuit 160, and the exclusive OR of these signals is taken. The output signal from this logic circuit 160 is
70 to logic circuit 140.

Similar to the embodiment shown in FIG. 1, in this embodiment, when a high level signal is applied from the input terminal 120 for a certain period of time, the count value of the up/down counter 110 becomes "HLH".
Indicates either “H” or “HHLL”. As long as the most significant digit of this count value is at high level, the output signal applied to output terminal 150 remains at high level. Therefore, even if noise enters the input signal, it will not affect the output signal as long as it is only for three clocks. This is due to the following reasons. First, the count value is "HLHH"
If low-level noise enters the state, the count value becomes "HLLL" at the third clock. Next, when a clock is applied, the count value becomes "LHHH" and the output signal of the most significant digit of the count value changes. Further, even when a low level signal is applied from the input terminal 120 for a certain period of time, noise up to three clocks can be removed.

FIG. 3 is an output diagram of the up/down counter 110 constituting the noise removal circuit of FIG. 2. In this figure, the output state changes in the 5th line, 11th line, 12th line, and 18th line from the top. The input state on the fifth line is that the input signal is a high level signal, and the up/down counter 110
The count value of is "LLLL". The logic circuit 160 includes output terminals Q2 and Q of the up/down counter 110.
Since the signal from 3 is input, the exclusive OR of the low level signal and the low level signal is taken, and a low level signal is output. This signal is changed to a high level signal by the inverting circuit 170 and is applied to the input of the logic circuit 140. Since the logic circuit 140 is also given a low level signal which is an inversion of the input signal, the exclusive OR of these is taken and a high level signal is output. Since this high level signal is given to the up/down counter 110,
The count value decreases by one and changes to "HHHH". Therefore, the output signal Q changes to a high level signal.

In the 11th line, when the input signal is a high level signal, the count value of the up/down counter 110 is "LHH".
H", the output of the logic circuit 140 becomes a low level signal. This low level signal is given to the up/down counter 110, so the count value increases by one.
Changes to "HLLL". Therefore, the output signal Q changes to a high level signal.

In the 12th line, when the input signal is a low level signal, the count value of the up/down counter 110 is "HLL".
Since the signal is at a high level, the output of the logic circuit 140 becomes a high level signal. This high level signal is given to the up/down counter 110, so the count value decreases by one.
It changes to "LHHH". Therefore, the output signal Q changes to a low level signal.

In the 18th line, when the input signal is a low level signal, the count value of the up/down counter 110 is "HHH".
H", the output of the logic circuit 140 becomes a low level signal. This low level signal is given to the up/down counter 110, so the count value increases by one.
Changes to "LLLL". Therefore, the output signal Q changes to a low level signal.

[0022]

As described above in detail, according to the present invention, when the first level input signal is continuously input, the count value of the up/down counter converges to the first reference value. . When the second level input signal is continuously input, the count value of the up/down counter converges to the second reference value.

[0023] If noise enters in a state where the count value of the up-down counter has converged to the first reference value or the second reference value, the count value will become an arbitrary value between the first reference value and the second reference value. Change the value in the direction closer to . However, since the output signal maintains a constant value unless the count value exceeds an arbitrary value, noise contained in the input signal can be removed.

Therefore, it is effective to use the circuit of the present invention in fields such as digital signal reproduction on low-speed transmission lines.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a noise removal circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a noise removal circuit according to an embodiment of the present invention.

FIG. 3 is an output diagram of an up/down counter.

FIG. 4 is a configuration diagram of a conventional noise removal circuit.

[Explanation of symbols]

10...Up/down counter 20...Logic circuit 30...Input terminal 40...Logic circuit 50...Clock terminal 60...Output terminal

Claims (1)

[Claims] Claim 1: In a noise removal circuit that removes noise contained in a binary input signal, a count value is increased when a first level signal is applied, and a count value is decreased when a second level signal is applied. a predetermined up-down counter that inputs the input signal and a signal indicating a count value of the up-down counter; a count control circuit that inverts the input signal and supplies it to the up-down counter when the input signal is equal to or less than a second reference value, and the count value of the up-down counter is selected between the first reference value and the second reference value. A noise removal circuit that outputs a first level signal when it is closer to a first reference value than any other arbitrary value, and outputs a second level signal when it is closer to a second reference value.