JPS5640251A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5640251A
JPS5640251A JP11648379A JP11648379A JPS5640251A JP S5640251 A JPS5640251 A JP S5640251A JP 11648379 A JP11648379 A JP 11648379A JP 11648379 A JP11648379 A JP 11648379A JP S5640251 A JPS5640251 A JP S5640251A
Authority
JP
Japan
Prior art keywords
sub mount
supporting base
mount
semiconductor chip
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11648379A
Other languages
Japanese (ja)
Inventor
Isao Hino
Kuniaki Iwamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11648379A priority Critical patent/JPS5640251A/en
Publication of JPS5640251A publication Critical patent/JPS5640251A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To reproducibly and effectively mount a semiconductor chip on a supporting base by heating by placing the semiconductor chip on a main supporting base through a sub mount adhering melted and adhered metallic films on both sides of the sub mount. CONSTITUTION:Cr 30, 32, AuSn alloys 31, 33 or the like are stacked on both upper and under surfaces of a sub mount 36 made of Cu or the like. A semiconductor chip 11, the sub mount 36 and a supporting base 22 are piled up for fixing and they are melted and adhered by heating. The chip will be mounted on the supporting base after cooling and starking. In this composition, melting and adhesion are applied at the same time and the second heat cycle is not applied between the semiconductor and the sub mount. Therefore, the length of the process will be reduced. Furthermore, melting and adhesion are entirely applied by metallic thin films formed by evaporation or the like. So, the control of film thickness is easy and a flat film will be formed. Therefore, the inclination of the element or sub mount or the shift of position will not cause and heat radiation is also good.
JP11648379A 1979-09-11 1979-09-11 Manufacture of semiconductor device Pending JPS5640251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11648379A JPS5640251A (en) 1979-09-11 1979-09-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11648379A JPS5640251A (en) 1979-09-11 1979-09-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5640251A true JPS5640251A (en) 1981-04-16

Family

ID=14688221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11648379A Pending JPS5640251A (en) 1979-09-11 1979-09-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5640251A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5966132A (en) * 1982-10-08 1984-04-14 Fujitsu Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5966132A (en) * 1982-10-08 1984-04-14 Fujitsu Ltd Manufacture of semiconductor device

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