JPS5630751A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5630751A
JPS5630751A JP10701879A JP10701879A JPS5630751A JP S5630751 A JPS5630751 A JP S5630751A JP 10701879 A JP10701879 A JP 10701879A JP 10701879 A JP10701879 A JP 10701879A JP S5630751 A JPS5630751 A JP S5630751A
Authority
JP
Japan
Prior art keywords
base
layer
type
withstand voltage
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10701879A
Other languages
Japanese (ja)
Inventor
Mamoru Fuse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10701879A priority Critical patent/JPS5630751A/en
Publication of JPS5630751A publication Critical patent/JPS5630751A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To contrive the reduction in the area of a chip by reducing the depth of a base without decreasing the withstand voltage of a semiconductor device by a base architecture formed of a high density region in a uniform and low density region. CONSTITUTION:An N type epitaxial layer 4 on a P type Si substrate 1 having an N<+> type buried layer 2 is isolated through P<+> type layer 3, 5. B ions are implanted to the layer 4 to form a first base layer 6 of density NB1, and a second base layer 7 of NB2>NB1 is subsequently formed. When a transistor which does not require high withstand voltage is formed only of the second base, the area of the chip can be reduced. Then, P type emitter layer 8 and N<+> type collector layer 9 are formed thereon. Since the gradient of the electric field E2 in the first base can be alleviated at this time, the withstand voltage thereof can be improved. As much as the base is formed of two-stage configuration, hFE and gain band width production fT can be aribitrarily selected. As a punch through to the emitter does not occur in the presence of the second base, the base can be consequently formed in shallow depth, and its withstand voltage can also be raised.
JP10701879A 1979-08-22 1979-08-22 Semiconductor device Pending JPS5630751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10701879A JPS5630751A (en) 1979-08-22 1979-08-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10701879A JPS5630751A (en) 1979-08-22 1979-08-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5630751A true JPS5630751A (en) 1981-03-27

Family

ID=14448417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10701879A Pending JPS5630751A (en) 1979-08-22 1979-08-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5630751A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48101885A (en) * 1972-04-03 1973-12-21
JPS4939307A (en) * 1972-08-12 1974-04-12
JPS502477A (en) * 1973-05-07 1975-01-11

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48101885A (en) * 1972-04-03 1973-12-21
JPS4939307A (en) * 1972-08-12 1974-04-12
JPS502477A (en) * 1973-05-07 1975-01-11

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