JPS5624634A - Key striking inspection system - Google Patents

Key striking inspection system

Info

Publication number
JPS5624634A
JPS5624634A JP10088279A JP10088279A JPS5624634A JP S5624634 A JPS5624634 A JP S5624634A JP 10088279 A JP10088279 A JP 10088279A JP 10088279 A JP10088279 A JP 10088279A JP S5624634 A JPS5624634 A JP S5624634A
Authority
JP
Japan
Prior art keywords
address
data
buffer
write
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10088279A
Other languages
Japanese (ja)
Inventor
Shuhei Inamori
Masatomo Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10088279A priority Critical patent/JPS5624634A/en
Publication of JPS5624634A publication Critical patent/JPS5624634A/en
Pending legal-status Critical Current

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  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To carry out the input processing including verify rapidly by detecting the delay accommodated address of the keys struck, comparing the accommodating contents of the two data buffer and checking.
CONSTITUTION: Back line address select portion 14 selects the back line address of the addresses indicated by the write address indicating portions 12, 13 (writing delayed side write address) and indicates it to the read data portion 15, 16. This expects the nonalignment of the keyboards 1 and 2 since for example, the data W1 is written in the first address of the buffer 7 and the data W2 is written in the second address. Then, at this time, the write data which can be compared by the comparison data 17 is only R1, R2 of the first address. Then, the information analyzer portion 18 receives the output of the circuit 17 and if they do not coincide, the signal NG is fed to the error processing portion 19 as any key operating being error and if it is normal, the signal OK is fed to the buffer full check 20.
COPYRIGHT: (C)1981,JPO&Japio
JP10088279A 1979-08-08 1979-08-08 Key striking inspection system Pending JPS5624634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10088279A JPS5624634A (en) 1979-08-08 1979-08-08 Key striking inspection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10088279A JPS5624634A (en) 1979-08-08 1979-08-08 Key striking inspection system

Publications (1)

Publication Number Publication Date
JPS5624634A true JPS5624634A (en) 1981-03-09

Family

ID=14285692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10088279A Pending JPS5624634A (en) 1979-08-08 1979-08-08 Key striking inspection system

Country Status (1)

Country Link
JP (1) JPS5624634A (en)

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