JPS59231789A - Memory device having data coincidence detection mechanism - Google Patents

Abstract

PURPOSE:To obtain a cache memory for retrieval of data which works at a high speed by adding a data coincidence detector for each ordinary memory cell as well as retrieval controller, an answer register and an address encoder to the outside area, respectively. CONSTITUTION:The retrieval data aj and mask data bj and fed in the form of a data input 21, and data aj and bj and delivered 25 by a retrieval controller 23. Then an address answer signal 28 showing the coincidence between the memory data and the retrieval data is obtained by a memory cell array 27 containing a data coincidence detector. The signal 28 is stored to an answer register 29 and encoded by an address encoder 31. The encoder 31 codes the minimum address among the detected address signals and obtains the address output of the minimum address. The signal 28 of the minimum address of the register 29 detected this time is reset by the address control signal 26. Thus the next small address is obtained. This procedure is repeated to detect at a high speed all addresses of the same contents as the retrieval data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device equipped with a data coincidence detection mechanism in a high-speed cache memory in a large-capacity memory system.

In general, large-capacity memory systems for large-scale computers use large-capacity but low-speed magnetic drums, due to the relationship between processing speed and capacity.
Memories such as magnetic disks are placed far from the CPU, medium-capacity and medium-speed IC memories are placed closer to the above-mentioned magnetic disks, and small-capacity but high-speed cache memories (also based on ICs) are located far from the CPU. It is configured to be placed nearby, and the high-speed cache memory is used for high-speed data search processing.

Conventionally, there has been an IC memory shown in FIG. 1 in such a large-capacity memory system.

In the figure, 1 is an address input, 2 is write data, 3 is an address decoder that decodes the address input 1, 4 is an address decode output output from the address decoder 3, and 5 is a memory cell array selected by the address decode output 4. , 6 are read data output from this memory cell array 5.

Next, the operation will be explained. At the time of memory writing, the address decoder 3 outputs an address decode output 4 in response to the address input 1, thereby writing the write data 2 into the designated memory cell.

Further, when reading the memory, the address decoder 3 outputs an address decode output 4 in response to the address input 1, whereby the contents of the designated memory cell are output as read data 6.

Conventional memory devices are configured as described above, so
In order to detect an address that stores a specific data pattern, it is necessary to sequentially change the address input and compare the read data with the specific data pattern. There were drawbacks such as the long time required for detection.

This invention was made to eliminate the drawbacks of the conventional ones as described above, and by adding a data coincidence detector to each memory cell, storing and encoding the detection results, it is possible to search for data. It is an object of the present invention to provide a memory device with a data coincidence detection mechanism that can obtain an address storing the data as an output when the data is input.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 2, 21 is a data input, 22 is a control input for instructing whether the data input 21 is write data or search data, 23 is a search controller that performs search control using the control human power 22 and the data human power 21, and 24 is the write data output from this search controller 23, 25
26 is the search data output from the search controller 23, 26 is the address control signal output from the search controller 23, and 27 is the search data output from the search controller 23.
28 is a memory cell array with a data coincidence detector, and 28 is an address response signal outputted from this memory cell array 27, which is outputted as many times as there are addresses of the memory cell array 27. 29 is a response register that latches this address response signal 28; 30 is a detection address signal output from this response register 29; 31 is an address encoder that encodes the minimum address of this detection address signal 30;
2 is an address output output from the address encoder 31, and 33 is an address empty signal output when all detected address signals are "0".

FIG. 3 shows details of the memory cell array 27 with data coincidence detector. In FIG. 3, 27' is a memory cell, and Sij is its stored information.

Further, Gl, G2 are NAND gates, G3. G4 is a NAND gate for bit storage forming a flip-flop; G5. G6. G7 is a NAND gate, Ai is an address line, W j (11, W j (o) is a write data line, Cj (o), Cj (1) is a search data line, the shoulder is a read data line, 40.41 is a resistor Here, the subscript i indicates the address, and the subscript j indicates the bit position.

Also, the numbers in parentheses represent bit information 0" or "1". Also, the difference from normal memory cells is that NAND gates G6 and G7 (data match detectors) and search data line Cj
To), Cj (11) and the response address line Ri are added.

Next, the operation will be explained. The operation when writing or continuously outputting data is the same as before. At this time, the write data is input as input data 21, and the search controller 23 receives this input data 21 and the control human power 22, and outputs the input data as write data 24.

On the other hand, when searching for data, search data a is used as data input.
j (1≦j≦m) and mask data bj (1515
m) is given. Here, the mask data is for masking bits that do not need to be compared among the m bits of search data a3, and for these bits, bj =
Set to 1. When both the above data aj and bJ are given, the data of each signal line in FIG. 3 is Wj(1)=Wj(o)=
0. Cj(1)=aj・bj, Cj(o)=aj
-bj, and at this time, the response signal Ri at address i in the memory cell array 27 is expressed by the following equation.

'=IT (bj +5ij-aj +5ij-aj
) That is, when the bit information 5ij (1≦jam) stored in the memory cell 27° and the bit information of the search data aj match for all bits other than "1" of the mask data bj, Ri=1.

As a result, an address response signal Ri for the input search data aj is output. Returning to FIG. 2, when the search data a3 and mask data bj are input as the data input 21, the search controller 23 outputs the search data aj, bj 25, and from this, Cj (
o), , Cj (11) is obtained, and from this, as explained in FIG. 3, an address response signal R128 indicating a match between stored data and search data is obtained from the memory cell array 27 with data match detector. This signal is stored in the response register 29 and encoded in the address encoder 31. Since the address encoder 31 encodes the smallest address of the detected address signal 30, it is possible to obtain the address output of the smallest address.

By the way, it is generally considered that there are a plurality of addresses stored in the response register 29. Therefore, in order to obtain the next address after the minimum address obtained this time, input the address obtained this time into address manual 1, and confirm that the address decode output 4 and data input 21 obtained at this time are also search data. The address control signal 26 outputted from the search controller 23 by the controller 22 shown in FIG. You can get the address of By repeating this process, all addresses having the same content as the search data can be detected at high speed.

According to the device of this embodiment having the above-described configuration, a normal memory cell is a NAND gate (G6. A high-speed data retrieval cache memory can be realized simply by adding G7, and although its capacity is reduced by adding NAND gate 06 and G7, it is still 1/2 compared to conventional IC memory.
It is possible to realize an IC with a capacity greater than that. Furthermore, in a large-capacity memory system, data throughput, that is, the time from inputting data to obtaining a processing result thereof, can be significantly improved.

In the above embodiment, in the response register 29, the register corresponding to the address read this time is reset by the combination of the address control signal 26 and the address decode output 40, but this is due to a circuit that prohibits output of this register. may be provided.

As described above, according to the present invention, a data match detector is added to a normal memory cell, and a search controller, response register, and address encoder are added externally, so that a high-speed data search cache is provided. Furthermore, it is possible to realize a cache memory IC with a capacity of 1/2 or more of that of a conventional IC memory, and furthermore, the data throughput in a large-capacity memory system can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional memory device, FIG. 2 is a block diagram showing a memory device with a data match detector according to an embodiment of the present invention, and FIG. 3 is an internal circuit of a memory cell with a data match detector. It is a diagram. 27...Memory cell array with data coincidence detector, G
6. G7...Gate (data match detector), 23...
- Search controller, 29...Response register, 31...Address encoder. In the drawings, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 Figure 3゛'1゛Portrait°'

Claims (1)

[Claims] (1) A memory cell array having a data match detector for each cell to detect a match between input search data and data stored in a memory cell at each address, and an address response signal line for each address; The present invention is characterized by comprising a search controller that supplies search data to the cell array, a response register for storing an address response signal from the memory cell array, and an address encoder that encodes address information from the response register. Memory device with data matching detection mechanism.