JPS5624630A - Plural input and output device control system - Google Patents
Plural input and output device control systemInfo
- Publication number
- JPS5624630A JPS5624630A JP10010079A JP10010079A JPS5624630A JP S5624630 A JPS5624630 A JP S5624630A JP 10010079 A JP10010079 A JP 10010079A JP 10010079 A JP10010079 A JP 10010079A JP S5624630 A JPS5624630 A JP S5624630A
- Authority
- JP
- Japan
- Prior art keywords
- control portion
- clk
- control system
- signal
- output device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To carry out the processing by one microprocessor and shorten the time by dividing one performance cycle into a plurality of small cycles and performing the common microprogram in parallel simultaneously.
CONSTITUTION: A plurality of I/O201, I/O202,... are controlled by the common control portion 30 including one set of the microprocessor μ PC and the respective I/O201, I/O202... performance cycle is divided into, for example, 4 small cycles and arranged in parallel with some small cycles spaced and slightly shifted from each other so that the microprogram will be preformed simultaneously. That is, from the control portion 30, I/O select signals AWD and the clock CLK are transmitted to I/O through the second bus and the detection information and the like after this performance are fed to the control portion 30 through the first bus. The first I/O control portion 221 receiving the signal A(a) and CLK (e) forms the signals AWD successively and at this time, the second I/O control portion 222 receives the signal B and CLK and similarly, in the order of B, C, D, A, forms the timing signal.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10010079A JPS5624630A (en) | 1979-08-06 | 1979-08-06 | Plural input and output device control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10010079A JPS5624630A (en) | 1979-08-06 | 1979-08-06 | Plural input and output device control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5624630A true JPS5624630A (en) | 1981-03-09 |
JPH0125094B2 JPH0125094B2 (en) | 1989-05-16 |
Family
ID=14264971
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10010079A Granted JPS5624630A (en) | 1979-08-06 | 1979-08-06 | Plural input and output device control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5624630A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5697130A (en) * | 1979-12-29 | 1981-08-05 | Hitachi Ltd | Input and output control processor |
JPS63307566A (en) * | 1987-06-09 | 1988-12-15 | Fujitsu Ltd | Channel device |
-
1979
- 1979-08-06 JP JP10010079A patent/JPS5624630A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5697130A (en) * | 1979-12-29 | 1981-08-05 | Hitachi Ltd | Input and output control processor |
JPS6217777B2 (en) * | 1979-12-29 | 1987-04-20 | Hitachi Ltd | |
JPS63307566A (en) * | 1987-06-09 | 1988-12-15 | Fujitsu Ltd | Channel device |
JPH0525335B2 (en) * | 1987-06-09 | 1993-04-12 | Fujitsu Ltd |
Also Published As
Publication number | Publication date |
---|---|
JPH0125094B2 (en) | 1989-05-16 |
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