JPS5621453A - Receiving margin confirming system - Google Patents

Receiving margin confirming system

Info

Publication number
JPS5621453A
JPS5621453A JP9767879A JP9767879A JPS5621453A JP S5621453 A JPS5621453 A JP S5621453A JP 9767879 A JP9767879 A JP 9767879A JP 9767879 A JP9767879 A JP 9767879A JP S5621453 A JPS5621453 A JP S5621453A
Authority
JP
Japan
Prior art keywords
margin
clock
receiving
data
transmitted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9767879A
Other languages
Japanese (ja)
Inventor
Nobuhiro Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9767879A priority Critical patent/JPS5621453A/en
Publication of JPS5621453A publication Critical patent/JPS5621453A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE:To receive transmission data by the receiving part to make it possible to confirm the receiving margin efficiently, by providing a margin clock, which has the phase changed by the receiving margin, in the transmission part in the communication control unit which transmits and receives data in the start-stop synchronizing system. CONSTITUTION:In bit transmission circuit 6, data 12 output from character decomposing part 8 is input to FF 12, and FF 11 is operated by reference clock 15 from switching circuit 14 or the clock from margin clock 13, and the output is transmitted to connection line l1, and sampling circuit part 5 performs sampling at the timing of clock 17 through connection line l1 folded to the receiving part, and receiving data is received by FF 11 and is transmitted to character assembling part 7. For the margin test of -45%, a distortion signal is transmitted by the margin clock which has the phase advanced by 45% for the reference clock and is sampled by the selection clock in the receiving side and is received correctly only with a margin of rest 5% for this selection clock, so that the margin of -45% can be confirmed.
JP9767879A 1979-07-31 1979-07-31 Receiving margin confirming system Pending JPS5621453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9767879A JPS5621453A (en) 1979-07-31 1979-07-31 Receiving margin confirming system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9767879A JPS5621453A (en) 1979-07-31 1979-07-31 Receiving margin confirming system

Publications (1)

Publication Number Publication Date
JPS5621453A true JPS5621453A (en) 1981-02-27

Family

ID=14198654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9767879A Pending JPS5621453A (en) 1979-07-31 1979-07-31 Receiving margin confirming system

Country Status (1)

Country Link
JP (1) JPS5621453A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63102433A (en) * 1986-10-17 1988-05-07 Sony Corp Inspecting device
JP2006303786A (en) * 2005-04-19 2006-11-02 Kawasaki Microelectronics Kk Data transmission reception circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63102433A (en) * 1986-10-17 1988-05-07 Sony Corp Inspecting device
JP2006303786A (en) * 2005-04-19 2006-11-02 Kawasaki Microelectronics Kk Data transmission reception circuit

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