JPS56158546A - Transmission and reception controlling circuit - Google Patents

Transmission and reception controlling circuit

Info

Publication number
JPS56158546A
JPS56158546A JP6143380A JP6143380A JPS56158546A JP S56158546 A JPS56158546 A JP S56158546A JP 6143380 A JP6143380 A JP 6143380A JP 6143380 A JP6143380 A JP 6143380A JP S56158546 A JPS56158546 A JP S56158546A
Authority
JP
Japan
Prior art keywords
circuit
signal
transmission
reception
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6143380A
Other languages
Japanese (ja)
Other versions
JPS6242544B2 (en
Inventor
Hiroshi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6143380A priority Critical patent/JPS56158546A/en
Publication of JPS56158546A publication Critical patent/JPS56158546A/en
Publication of JPS6242544B2 publication Critical patent/JPS6242544B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/20—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Bidirectional Digital Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To receive the burst signal regardless of the amount of a transmission delay time, by providing a circuit controlling the start and end of communication, reception synchronism holding state discriminating circuit, counting circuit, etc. for reception enabling time setting to a central control device. CONSTITUTION:A gate 12 is opened with a signal 20 from a signal controlling circuit 9 and a signal 21 giving a transmission time at the request of communication start, a transmission circuit 5 is controlled, and a transmission burst signal 23 is transmitted to a two line type transmission line 3. In this case, a selection circuit 10 selects the signal 21 and gives it to a gate 11 to make a reception circuit 4 receptable for the time other than a transmission time. The reception burst signal received at the circuit 4 is inputted to a burst synchronism bit extracting circuit 6 and a synchronism discriminating circuit 8. In the circuit 6, a burst synchronism signal 15 is outputted at a counting circuit 7, where counting is made in synchronizing with the signal 15, and a signal 16 giving the reception time is outputted to the circuit 10 and a decode signal 17 is outputted to a circuit 8. In the circuit 8, when the signal 17 feeds a synchronism holding signal 18 to the circuit 10, the circuit 10 selects the signal 16 to give the reception time to circuit 4 accordig to the transmission delay time.
JP6143380A 1980-05-09 1980-05-09 Transmission and reception controlling circuit Granted JPS56158546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6143380A JPS56158546A (en) 1980-05-09 1980-05-09 Transmission and reception controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6143380A JPS56158546A (en) 1980-05-09 1980-05-09 Transmission and reception controlling circuit

Publications (2)

Publication Number Publication Date
JPS56158546A true JPS56158546A (en) 1981-12-07
JPS6242544B2 JPS6242544B2 (en) 1987-09-09

Family

ID=13170923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6143380A Granted JPS56158546A (en) 1980-05-09 1980-05-09 Transmission and reception controlling circuit

Country Status (1)

Country Link
JP (1) JPS56158546A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5949034A (en) * 1982-09-14 1984-03-21 Nec Corp Receiving circuit for burst type bidirectional digital transmission
JPS5958933A (en) * 1982-09-28 1984-04-04 Nec Corp Receiving circuit of bidirectional burst digital transmission
JPS6295040A (en) * 1985-10-21 1987-05-01 Nec Corp Time division bidirectional communication system
JPS62219839A (en) * 1986-03-20 1987-09-28 Oki Electric Ind Co Ltd Starting control system
JP2007046716A (en) * 2005-08-10 2007-02-22 Hitachi Ltd Rotation-linear motion converting mechanism and its manufacturing method

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62152939U (en) * 1986-03-22 1987-09-28
JPH0542036Y2 (en) * 1986-04-21 1993-10-22
JPH0427786Y2 (en) * 1986-04-21 1992-07-03

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5949034A (en) * 1982-09-14 1984-03-21 Nec Corp Receiving circuit for burst type bidirectional digital transmission
JPS5958933A (en) * 1982-09-28 1984-04-04 Nec Corp Receiving circuit of bidirectional burst digital transmission
JPS6295040A (en) * 1985-10-21 1987-05-01 Nec Corp Time division bidirectional communication system
JPS62219839A (en) * 1986-03-20 1987-09-28 Oki Electric Ind Co Ltd Starting control system
JP2007046716A (en) * 2005-08-10 2007-02-22 Hitachi Ltd Rotation-linear motion converting mechanism and its manufacturing method

Also Published As

Publication number Publication date
JPS6242544B2 (en) 1987-09-09

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