JPS5958933A - Receiving circuit of bidirectional burst digital transmission - Google Patents

Abstract

PURPOSE:To reduce the effect of switching noise without using a switch having less switching noise, by providing a discriminating circuit performing the discrimination only at the 2nd receiving period having slower phase for start of receiving than the phase of the 1st receiving period, and having a length being a burst length or over of a receiving burst signal. CONSTITUTION:The receiving burst signal R from a transmission line 8 is applied to a receiving circuit 10 via a transformer 7. A signal on the transmission line 8 is shown in Fig. (b) in this case. The receiving burst signal R of the receiving circuit 10 is inputted to a buffer amplifier 13 via a switch 11 conductive at the receiving period of high level of a control signal 12 as shown in Fig. (c). A buffer amplifier 13 amplifies switch noise as shown in hatched lines as well as the receiving burst signal R as shown in Fig. (d). The output of the buffer amplifier 13 is applied to a discriminating circuit 14. The discriminating circuit 14 is operative only at the receiving period of the high level with a control signal 15 as shown in Fig. (e) slower in the phase of start of receiving than the receiving period given by the control signal 12.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving circuit for bidirectional burst type digital transmission.

The digitalization of communication systems is expanding, and research and development is also underway regarding the digitalization of subscriber lines72.667@
There is a bidirectional burst type digital transmission system described above. A schematic block diagram of a transmission path interface circuit in such a transmission system is shown in FIG.

The timing waveform diagram is shown in Figure 2. The transmission line interface circuit in Figure 441 consists of transmitting circuit 1, receiving circuit 2,
The transmission burst signal S blocked in the transmission circuit 1 is sent to the transmission line 4 by turning on the switch 3 to the transmission circuit 1 side during the transmission period shown in FIG. 2(a). Then, by turning on the receiving period switch 3 shown in FIG. 2(c) on the receiving circuit 2 side, the receiving burst signal R from the transmission line 4 is supplied to the receiving circuit 2. The signal on the transmission line 4 at this time is shown in FIG. 2 (bl).

As shown in FIG. 2 (d), the receiving circuit 2 is supplied with switch noise (indicated by diagonal lines) caused by the switch 3 being turned on to the receiving circuit 2 side, in addition to the received burst signal. If the distance of 4 is long, the level of this switch noise will be the same as the level of the received burst signal 1t, which may cause erroneous reception. Therefore, an expensive switch with low switch noise is required. This poses a problem in terms of the economy of 9 letters and 6 messages.

The purpose of the present invention is to provide a more economical communication device in which the switch noise of the switch (1) is not negligible compared to the level of the received signal, and the influence on the received signal is minimized. be.

A receiving circuit for bidirectional burst digital transmission according to the present invention includes a buffer amplifier that buffers a received burst signal;
a first switch circuit provided at an input stage of the buffer amplifier and supplying the received burst signal to the buffer amplifier only during a first reception period set to receive the received burst signal; and an identification circuit that performs all identification only during a second reception period in which the reception start phase is later than the reception period and the length is longer than the burst length of the received burst signal.

Next, the present invention will be described in detail with reference to the drawings. Third
The figure shows an embodiment of a transmission line interface circuit having a receiving circuit according to the present invention. The entire operation of this embodiment will be explained using the timing chart shown in FIG. The transmission burst signal S blocked in the transmission circuit 5 is supplied to the driver 6, and the driver 6 connects the reception burst signal hole of the high level transmission of the control signal 9 shown in FIG. 4(a) to the reception circuit via the transformer 7. IO is supplied. The signal on the transmission line 8 at this time is shown in FIG. 4(b). In the receiving circuit 10, as shown in FIG.
The reception burst signal R is input to the buffer amplifier 13 via the switch 11 which is turned on during the reception period when the control signal 12 is at a high level indicated by C1. The buffer amplifier 13 amplifies the received burst signal Ri as shown in FIG. 4(d), but at the same time also amplifies the switch noise shown by diagonal lines. The output of this buffer amplifier 13 is supplied to an identification circuit 14.

The identification circuit 14 is. The control signal 15 shown in FIG. 4(e) whose phase of start of p reception is later than the reception period given by the control signal 12 causes the device to be in an operating state only during the high level reception period.

Therefore, since the switch noise is not discriminated as shown in the fourth [19 (fl), the influence of the switch noise can be reduced, and the discriminator circuit 14 uses the digital Only the signal R" is output.

FIG. 5 shows an example of the configuration of the identification circuit 14 in the m3 diagram. Fifth
The identification circuit 14 in the figure is a peak value holding circuit that holds the peak value and outputs the threshold IK' for identification, and receives the obtained threshold value to the negative input and inputs the single strike signal to the positive input, respectively. The comparator 22 outputs a digital value, and the 1LND gate 23 outputs the output of the comparator 22 as a discrimination result only during the period when the control signal 17 is at the /% low level. Note that when the received burst signal is a double-current code, a full-wave rectifier circuit 24 shown by a broken line is provided at the input stage.

FIG. 6 shows another embodiment of the receiving circuit of the present invention.

This embodiment is the same as the receiving circuit 10 of FIG. 3 using the discriminating circuit 14'fc of FIG. 5, except that a switch 25 is provided at the input of the peak value holding circuit 21 of the discriminating circuit 14. The operation of this embodiment will be explained using the timing chart shown in FIG. In addition, the control shown in FIG. 4B+j15.The phase of the start of reception of the control signal 16 shown in FIG. 7(cl) is later than the phase of the start of reception of the control signal 12 shown in FIG.
) is faster than the reception-@start phase of the control signal 15 shown in FIG.

Since the switch 25 is conductive only during the reception period of the control signal 16, the component of the switch noise supplied to the peak value holding circuit 21 becomes extremely small as shown by diagonal lines in FIG. 7(d). Therefore, the total effect of the switch noise of the switch 11 on the threshold 1 output from the peak value holding circuit 21 is small.9. The identification circuit 14 can perform more stable identification.

As described above, according to the present invention, it is possible to reduce the influence of switch noise without using switches with low switch noise, and to create a receiving circuit for bidirectional burst type digital transmission that has good communication quality and is economical. can be provided.

[Brief explanation of the drawing]

FIG. 5 is a timing diagram showing the operation of the Hue-12 circuit; FIG. 3 is a timing diagram showing the operation of FIG. 3; and FIG. 5 is a block diagram showing a configuration example of the identification circuit of the embodiment shown in FIG. FIG. In the figure, 1.5 is the transmitting circuit, 2.10 (,b
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(C) 4.8 is a transmission line, 6 is a driver, 7 is a transformer, 13 is a buffer amplifier, 14 is an identification circuit, (d: 21 is a peak value holding circuit, 22ri comparator, 23 is an AND gate, 24 is a folding board) Shows the flow circuit. Shino Uchihara, a famous patent attorney) Mouth 2 Entai 3 Roo 44 (f) R'7+S
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Claims (1)

[Scope of Claims] A buffer amplifier that receives a received burst signal, and a buffer amplifier that is provided at an input stage of the buffer amplifier and is set to receive the received burst signal, and that transmits the received burst signal only during a first reception period. a first switch circuit that supplies the buffer amplifier; and an identification circuit that performs all identification only in a second reception period in which the reception start phase is later than the first reception period and the length is longer than or equal to the burst length of the received burst signal. A receiving circuit for bidirectional burst type digital transmission, characterized in that: