JPS5549055A - Synchronization system - Google Patents

Synchronization system

Info

Publication number
JPS5549055A
JPS5549055A JP12152278A JP12152278A JPS5549055A JP S5549055 A JPS5549055 A JP S5549055A JP 12152278 A JP12152278 A JP 12152278A JP 12152278 A JP12152278 A JP 12152278A JP S5549055 A JPS5549055 A JP S5549055A
Authority
JP
Japan
Prior art keywords
signal
output
synchronizing
reception
timing signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12152278A
Other languages
Japanese (ja)
Inventor
Takeo Kusama
Hisashi Kiyonaga
Junji Iwatake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12152278A priority Critical patent/JPS5549055A/en
Publication of JPS5549055A publication Critical patent/JPS5549055A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To simplify synchronization between a reception timing signal and received data by sending synchronizing codes of a transmission timing signal and then by synchronizing the reception timing signal by detecting rise change points of synchronizing codes at a reception side. CONSTITUTION:On reception of transmission request signal 1 from a data terminal equipment, etc., an carrier output from modulator 2 is sent out to transmission line 3. Then, delay switching circuit 4 starts operating and after a certain time for data link establishment between modems passes, gate signal 5 appears at its output. Consequently, synchronizing signal 7 is gated from transmission timing generating circuit 6 so as to obtain gate output 8. By output 8, transmitted data 13 is inputted as transmitted signal S to sample holding circuit 9 and sampled and held as output 9' by sampling pulse 10; and it is modulated by modulator 2 and sent out to transmission line 3. Consequently, the reception timing signal can be synchronized with received data.
JP12152278A 1978-10-04 1978-10-04 Synchronization system Pending JPS5549055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12152278A JPS5549055A (en) 1978-10-04 1978-10-04 Synchronization system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12152278A JPS5549055A (en) 1978-10-04 1978-10-04 Synchronization system

Publications (1)

Publication Number Publication Date
JPS5549055A true JPS5549055A (en) 1980-04-08

Family

ID=14813299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12152278A Pending JPS5549055A (en) 1978-10-04 1978-10-04 Synchronization system

Country Status (1)

Country Link
JP (1) JPS5549055A (en)

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