JPS55128953A - Reception distortion control method for start-stop synchronous system - Google Patents

Reception distortion control method for start-stop synchronous system

Info

Publication number
JPS55128953A
JPS55128953A JP3669379A JP3669379A JPS55128953A JP S55128953 A JPS55128953 A JP S55128953A JP 3669379 A JP3669379 A JP 3669379A JP 3669379 A JP3669379 A JP 3669379A JP S55128953 A JPS55128953 A JP S55128953A
Authority
JP
Japan
Prior art keywords
reception
circuit
mupu3
given
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3669379A
Other languages
Japanese (ja)
Other versions
JPS6033326B2 (en
Inventor
Junzo Okunaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP54036693A priority Critical patent/JPS6033326B2/en
Publication of JPS55128953A publication Critical patent/JPS55128953A/en
Publication of JPS6033326B2 publication Critical patent/JPS6033326B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits

Abstract

PURPOSE:To secure the assured correction for the reception distortion throhgh the simple control, by securing the variable timing for the middle point sampling of the ST (start) bit based on the indication given from the external control switch. CONSTITUTION:Level conversion circuit 1 decides stop polarity (logic 1) and start polarity (logic 0) each and then transmits them to reception circuit 2. And circuit 2 sends these polarities to microprocessor muPU3 after giving matching with the logic level equivalent to muPU3. Then muPU3 receives the designation for the clock number in terms of the ST bit of the middle point sampling SPT given from switch part 5 and then performs the reception and distribution for the start-stop synchronous serial reception signals from circuit 2 to the parallel information. At the same time, the control is given so that the serial reception signals may be delivered to output unit 4 like the printer, the paper tape punch and the like. As a result, the assured control is possible for the reception distortion.
JP54036693A 1979-03-28 1979-03-28 Receiving distortion adjustment method for asynchronous system Expired JPS6033326B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54036693A JPS6033326B2 (en) 1979-03-28 1979-03-28 Receiving distortion adjustment method for asynchronous system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54036693A JPS6033326B2 (en) 1979-03-28 1979-03-28 Receiving distortion adjustment method for asynchronous system

Publications (2)

Publication Number Publication Date
JPS55128953A true JPS55128953A (en) 1980-10-06
JPS6033326B2 JPS6033326B2 (en) 1985-08-02

Family

ID=12476874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54036693A Expired JPS6033326B2 (en) 1979-03-28 1979-03-28 Receiving distortion adjustment method for asynchronous system

Country Status (1)

Country Link
JP (1) JPS6033326B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923646A (en) * 1982-07-29 1984-02-07 Matsushita Electric Ind Co Ltd Bit clock regenerating device
JPS60126941A (en) * 1983-12-13 1985-07-06 Oki Electric Ind Co Ltd Code synchronization system
JPS61100038A (en) * 1984-10-23 1986-05-19 Nec Corp Digital phase synchronizing circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6243335U (en) * 1985-09-02 1987-03-16

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5923646A (en) * 1982-07-29 1984-02-07 Matsushita Electric Ind Co Ltd Bit clock regenerating device
JPH0125460B2 (en) * 1982-07-29 1989-05-17 Matsushita Electric Ind Co Ltd
JPS60126941A (en) * 1983-12-13 1985-07-06 Oki Electric Ind Co Ltd Code synchronization system
JPH0568136B2 (en) * 1983-12-13 1993-09-28 Oki Electric Ind Co Ltd
JPS61100038A (en) * 1984-10-23 1986-05-19 Nec Corp Digital phase synchronizing circuit

Also Published As

Publication number Publication date
JPS6033326B2 (en) 1985-08-02

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