JPH0125460B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is particularly applicable to an apparatus for recording and reproducing audio PCM signals in a format compliant with standard television signals using a helical scan system using a rotating head. During playback, etc.
This invention relates to a bit clock reproducing device that has followability that can cope with jitter occurring in PCM signals.

Configuration of conventional example and its problems Since the digital signal reproduced from the tape by helical scan is in a format that conforms to the standard television signal (see Japanese Patent Publication No. 30707/1983, etc.), a predetermined synchronous It is necessary to take out the signal and also take out another data signal. This data signal is extracted by slicing the reproduced signal at a predetermined level and then detecting the "value" of each bit using a pulse whose width is sufficiently narrower than one bit of the data signal.
This is sometimes called "punching of data signals." In order to perform this "punching" reliably,
The sufficiently narrow pulse (hereinafter referred to as the bit clock signal) must be located approximately at the center of each bit. However, due to various mechanical factors, the reproduced data signal usually contains jitter, and the bit clock signal is often not located at the center of each bit. Conventionally, it has been possible to punch out data signals by applying complex feedback to the rotating head and tape running system to suppress jitter, but other methods have been developed to further improve accuracy and obtain high-quality playback signals. was desired.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a bit clock reproducing device that obtains a bit clock signal that changes in accordance with the data signal so that the data signal in the reproduced PCM signal is cut out approximately at the center of the data signal. It is something to do.

Structure of the Invention The present invention inputs a data signal in a reproduced PCM signal, detects the center part of the bit of this data signal, and detects the position of the center part of the bit and the position of a clock signal for punching. This bit clock reproducing device is configured to compare the relative relationship, vary the position of the clock signal, and generate a clock signal for punching that follows the data signal.

DESCRIPTION OF THE EMBODIMENTS FIG. 1a shows a portion of a data signal obtained by slicing a reproduced PCM signal at a certain level. FIG. 1b is a diagram showing one bit in a data signal and a master clock signal having a frequency six times that bit.

Fig. 2 is a block diagram of one embodiment of the present invention;
The figure is a specific circuit diagram. A is a data signal containing jitter, and C is the master clock signal. 1 is the bit center detection section,
The center portion (bit center) of each bit of the data signal A is detected. 2, 3, and 4 are center comparators, which output the output of the bit center detection section 1;
The difference between the bit center and the position of the bit clock to be punched is generated by the output of the 1/6 frequency divider 5. The outputs of these center comparators and the master clock signal C are input to a 1/6 frequency divider 5 to generate a bit clock signal B located at the center of each bit.

Next, the operation of the circuit of the embodiment will be explained in detail using FIG.

() Assuming that data signal A is a continuous “0” or “1”, (1-1) If data signal A is a continuous “0” input signal, the output of FF11 is , “1” The output of FF12 is “1” The output of FF13 is “1” The Q output of FF14 is “0” The Q output of FF15 is “0” The Q output of FF16 is “0” Then,
The output of NOR17 continues to output "0". (1
-2) When data signal A is a continuous “1” input signal, the output of FF11 is “0” The output of FF12 is “0” The output of FF13 is “0” Q output of FF14 is “1” Q output of FF15 is “1” Q output of FF16 is “1”, therefore,
The output of NOR17 continues to output "0".

In this way, when data that changes the input data signal does not arrive, the output of the NOR 17 always holds "0". In this state, the circuit shown in FIG. 3 equivalently becomes the circuit shown in FIG. 4, and a signal whose frequency is divided by 1/6 of the master clock is output as the bit clock signal B. The details are shown below.

In other words, if the output of NOR17 is “0”, (a) the output of NAND32 is “1”, and the FF
The output of 26 becomes "0".

At this time, the XOR 33 outputs the output of the FF 21 as is, and transmits it to the input of the FF 22.

Similarly, the XOR 34 also outputs the output of the FF 22 as it is, and transmits it to the input of the FF 23.

The OR36 also outputs the output of the FF24 as it is, and also transmits it to the input of the FF25.

Therefore, NAND32, FF26, XOR3
3, 34, and OR36 can be considered to be non-existent in terms of operation.

(b) The output of NAND27 becomes “1” and FF
The output of 18 becomes "1".

Also, the output of NAND30 becomes “1”,
NAND29 inverts the output signal of INV28 and transmits it to the input of FF19.
Therefore, since the output of NOR31 is input to the input of INV28, operationally, NOR
It can be considered that the output of 31 is directly input to the input of FF19.

Therefore, NAND27, 29, 30, FF1
8, INV28 may be considered to be in a non-operational state.

(c) In terms of these operating states, FIG. 3 is equivalent to FIG. 4.

Therefore, the bit clock signal B is a signal obtained by dividing the master clock C by 1/6.

FIG. 5 shows the operation timing of the circuit shown in FIG. 4. That is, bit clock signal B is
A signal obtained by dividing the master clock signal C by 1/6 is output.

() When the next applied data signal A changes from "0" to "1", when "1" for three clocks of the master clock signal C arrives, the output of NOR17 at the timing shown in FIG. It becomes “1”.

At this time, let us consider the combinations when the conditions are in the sections , , , in Fig. 5.
When the output of NOR17 is "1"... When the Q output of FF20 is "0" ... When the Q output of FF20 is "1" ... When the output of NOR31 is "1" , ...When the Q output of FF19 is "1", it will be explained separately.

Operation in section () When the output of NOR17 becomes “1”, the Q output of FF20 becomes “1” in the next master clock signal.
Since it is "0", the output of the FF 26 remains "0". XOR33,34,OR3 at that time
The operation of No. 6 is the same as described above. Also FF19
Since the Q output of is also "0", the output of NAND30 also remains "1". Moreover, since the output of NOR31 is also "0", the output of NAND27 remains "1", and the output of FF18 also remains "1". Therefore, in this case as well, NOR
The output of 31 is transmitted to the input of FF19.

Overall, the operation is similar to that shown in FIG. 4, and the relationship among data signal A, bit clock signal B, and master clock C is as shown in FIG. 7, and there is no change in frequency of bit clock signal B.

At this time, the relationship between the Q output of the FF37 and the bit clock signal B is as shown in FIG.
4, the position is B5. That is, data signal A
When the bit clock signal B is generated at each bit position B3, B4, B5, the bit clock signal B is punched out by the FF 38 without being subjected to frequency (generation position) control. The Q output D of the FF 38 indicates the punched data signal.

Operation in the section () When the output of NOR17 becomes “1”, FF2
When the Q output of 0 is “1”.

(A) The Q output of FF26 becomes “1” at the next master clock. At that time, XOR33 and
XOR34 will perform INV operation,
Q output of FF21 is inverted and output to FF22
The Q output of FF22 is inverted and transmitted to input D of FF23. Also
The output of OR36 becomes "1" and becomes the input of D of FF25. This is because the output of NOR17 becomes “1” and 2 master clocks later, FF2
This shows that the Q output of 5 becomes "1".

(B) Since the Q output of FF19 is “0”
The output of NAND30 remains "1".
Since the output of NOR31 is “0”
The output of NAND27 remains "1".
Therefore, the Q output of FF18 also remains "1", and the output of NOR31 is transmitted as is to the D input of FF19.

The relationships at this time are as shown in FIG. 12. Originally, the bit clock position of B6 was scheduled to be 1.
The bit clock position will move to B5 earlier by the master clock. That is, in the above example, the bit clock moves to position B5, which is closer to the center of the bit.

In this way, it can be seen that the bit clock signal B operates one master clock cycle earlier than the bit clock signal before correction.

Operation in the section () When the output of NOR17 becomes “1”, NOR
When the Q output of FF31 is “1” (A) Since the Q output of FF20 is “0”,
NAND32, FF26, XOR33,34,
OR36 is operationally the same as not being present.

(B) Since the Q output of FF19 is “0”,
The output of NAND30 is “1”, and FF18
Since the Q output of is “1”, also at this time
The output of NOR31 is directly transmitted to the D input of FF19. The output of NAND27 is “0”
Then, the next master clock signal turns FF.
The Q output of FF18 becomes “0” and the output of NAND29 is inverted and becomes “1”, and the D of FF19
transmitted to the input. For the D input of FF19,
The signal becomes "1" by two master clocks, and the divided output is delayed by one master clock.

Therefore, in FIG. 12, the bit clock position of B2 will be moved to B3 in the next data signal.
That is, in the above example, the bit clock signal is moved to the position B3, which is closer to the center of the bit.

Operation in the section () When the output of NOR17 becomes “1”, FF1
When the Q output of 9 is “1” (A) Since the Q output of FF20 is “0”,
NAND32, FF26, XOR33,34,
OR36 is operationally the same as none.

(B) Since the Q output of FF19 is “1”,
The output of NAND30 becomes “0”,
The output of NAND29 becomes "1". Therefore,
The Q output of FF19 also becomes "1" at the next master clock. Also, the output of NOR31 is
Since it is “0”, the output of NAND27 is “1”
Then, at the next master clock, FF
The Q output of 18 is "1".

Therefore, in FIG. 12, the bit clock position of B1 moves to B2 for the next data signal, and further moves to converge at B3 for the next data signal as explained above. go.

The above operations are collectively shown in a waveform diagram as shown in FIG. 11.

As described above, in the present invention, the central part of the bit of the data signal is detected, the relative position with respect to the bit clock signal for punching is detected, and the position of the bit clock signal is changed based on the detection output, so that the position of the bit clock signal is changed. By controlling the bit clock signal so that it is located in the center, the bit clock signal can always follow even data signals containing jitter.
Punching is always possible near the center of the bit.

Note that FIG. 13 shows another example of the circuit configuration, and circuits that are the same as those in FIG. 3 are given the same numbers. The configuration shown in FIG. 13 performs the operation of converging the bit clock position near the center of the bit in exactly the same way, but has the feature of being simpler.

Effects of the Invention The present invention detects the center of a bit of a data signal, detects its position relative to the bit clock signal for punching, and uses the detection output to change the position of the bit clock signal so that it is located at the center of the bit. By controlling the position so that the bit clock signal always follows even data signals containing jitter, punching can always be performed near the center of the bit, and a high-quality reproduced data signal can be obtained. This provides an excellent bit clock reproducing device.

[Brief explanation of drawings]

FIG. 1a is a waveform diagram showing the data signal of the reproduced PCM signal, FIG. 1b is a waveform diagram showing the time width of one bit of the data signal and the master clock signal, and FIG. A block diagram showing one embodiment, Fig. 3 is a specific circuit diagram of this embodiment, Fig. 4 is an equivalent circuit diagram in a state where the bit clock is output in free run, and Figs. FIG. 12 is a waveform diagram for explaining the operation of the embodiment, FIG. 12 is a diagram for explaining the relative position of one bit of the data signal to be punched out and the bit clock to be punched out, and FIG. 13 is a circuit diagram of another embodiment. 1... Bit center detection section, 2, 3, 4...
Center comparator, 5...1/6 frequency divider.

Claims (1)

[Claims] 1 Compliant with the reproduced standard television signal
Means for inputting a data signal in a PCM signal, detecting the center part of a bit of the data signal, the center part of the detected bit, and one bit of the data signal for punching out the data signal. Comparing means compares the relative relationship of each position with the bit clock signal to be divided and generates a detection output, and inputs the detection output of this comparison means and controls the master clock signal to generate the bit clock signal located at the center of the bit. 1. A bit clock reproducing device comprising means for forming a bit clock.