JPS61100038A - Digital phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To obtain a phase synchronizing circuit suitable for circuit integration by constituting generation of a clock synchronously with an identified digital signal only with a digital circuit. CONSTITUTION:A comparator 1 compares a transmitted waveform with a refer ence voltage source 2 and applies a digital value formed to a shift register 3. The register 3 is activated by using a local clock having a frequency higher than that of a transmission clock from a local clock generator 9, the identified digital signal is subject to multi-point sampling and each stage output of the value is inputted to a center position detection circuit 5. The circuit 5 detects a phase synchronizing signal 5-1 from an output signal of each stage from the register 3 by the circuit 5 and fed to a phase circuit 20. When the circuit 20 applies the signal 5-1 to a counter circuit 19, the circuit 19 counts a pre scribed number of local clocks from a generator 9 and gives its output to a latch circuit 4. The circuit 4 latches a Q10 output of the register 3 when the sampling value of the medium of the digital signal subject to multi-point sam pling is outputted from the register 3 and reproduces correctly a reception signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital transmission device, and particularly to a phase synchronization circuit for a digital transmission device using a return-to-zero transmission code.

(Prior art and its problems) A digital phase synchronization circuit synchronizes a transmitted signal with a clock of a receiving device.
There is a specification ``Clock Extraction Circuit'' in Japanese Patent No. 178512.

In such prior art, the extremely thick position of the received transmission waveform is detected and the phase of the counting circuit is controlled at the time of detection.

In such prior art, a differentiating circuit using an analog operational amplifier is used to detect the maximum position of the transmitted waveform. However, when an analog operational amplifier is integrated into an integrated circuit, it has a disadvantage in terms of the degree of integration compared to a digital circuit.

(Object of the Invention) An object of the present invention is to provide a digital phase locked circuit that does not require an analog operational amplifier and is suitable for integration into an integrated circuit.

(Structure of the Invention) The digital phase synchronized circuit of the present invention includes a local clock generator that generates a local clock with a frequency higher than a transmission frequency, and a system that samples a received transmission code identified as a binary signal using the local clock and receives the received transmission code. A shift register that stores sample values for one cycle or more of a transmission code is input, and the parallel outputs of this shift register are input, and the center sample value of the sequence of continuous sample values of discrimination level 1 is determined by the predetermined value of the shift register. a central position detection circuit that detects that the output stage has been reached and outputs a phase synchronization signal; a counting circuit that operates with a clock during the interval h1; and a phase control that controls the counting operation of the counting circuit based on the phase synchronization signal. It consists of a circuit.

(Example) The configuration of a digital phase synchronization circuit according to the present invention is shown in FIG. This digital phase synchronization circuit includes a comparator 1. Shift register for multi-point sampling of the identified digital signal3. Transmission lock of the received signal - A latch circuit 4 that latches with a synchronized clock, a center position detection circuit 51 that detects the center position of the discrimination level 1 signal sampled at multiple points, and a phase control circuit 20. It is comprised of a local clock generator 9 that generates a local clock with a frequency higher than the transmission frequency of the received signal, for example eight times as high, and a counting circuit 19 that generates a clock synchronized with the transmission lock.

A first embodiment of the present invention will be described with reference to FIG. 1 and FIGS. 2(a) to (j). The comparator 1 compares the transmission waveform shown in FIG. 2(a) with the voltage VR of the reference voltage source 2, and inputs the digital value shown in FIG.
Supply to N. In addition, in the same figure, 1.1.0°1.01,
An example corresponding to one digital signal is shown. The local clock generator 9 generates a local clock having a frequency eight times that of the transmission lock (FIG. 2(C)). This local clock is shown in the same figure (d). The shift register 3 is operated by this local clock inputted to the clock input CP,
The identified digital signal is multi-point sampled. The shift register 3 has a 10-hit configuration, for example, in order to store sample values for one period or more of the transmission signal. The signal of the first stage output Q of this shift register 3 is
The stage output Q is shown in the same figure (f). The center position detection circuit 5 inputs the 10-bit output from each stage of the shift register 3, and supplies the phase synchronization signal 5-1 shown in FIG. 2(g) to the phase control circuit 20.

The process of generating this phase synchronization signal will be explained below. 1
The 0-bit shift register 3 samples the digital signal shown in FIG. 2(b) at multiple points, in this case at 8 times the frequency. The central stage of the shift register 3, that is, the fifth stage (output stage Q
At a), the central position of the pulse of discrimination level 1 arrives at the sample value shown in FIG.
This is when it is output to Q+o. That is, 1 continues from the output stage Q toward the lower output stage Q4...Q.
The number of output stages from output stage Q6 to upper output stage Q7...+
This is a case where the number of consecutive 1's toward Q+o is the same or one more. The detection circuit 5 converts this pattern into a NOR gate 8° decoder 6. F, AND gate 1
1, 12, 13, 14, 15゜16.17.18 and O
Detected by R gate 10.

NOR gate 8 is output stage Q1Q of shift register 3,
. When both are O, set the output level to 1, and
Supply to Enable Human Power EN of 7. Decoder 6 includes output stage Q2. Input Qs, Q4 and Q, and obtain Q shown in Figure 3.
2 Q5 four patterns P+t+PI21PISr
Output 6-1.6 corresponding to each time PI4 appears
-2.6-3.6-4 to logic level 1.

Similarly, Teco-Tough inputs the output stage Q=-Qt, Qs, Qo and generates the five patterns P2 of Qa Qo shown in FIG.
Ir Ptt + P23! When P24 + Pts appears, the corresponding output cuff -1, 7 - 2, 7
Set -3, 7-4, and 7-5 to logic level 1. Therefore,
Ql-Q,. The pattern of P I+ P 21 P s
+ P 41 “”” l P s is shift register 3
AN corresponding to each pattern when output from
D Kate 11, 12. 13, 14. ......, 18
The output of will be a logic level 1. This signal is OR gate 1
0 to the phase circuit 20 (this is supplied as a phase synchronization signal 5-1).

This phase synchronization signal 5-1, ie, the pulse signal shown in FIG. 2(g), is supplied as is to the storage control input LD of the counting circuit 19. The counting time Pr19 inputs the value determined by this signal as data input, ,D, ,D.

(DI is the higher bit) value is stored. In this example,
D, = 1. D2 = 1. D3 = 1, therefore, the counting circuit 19 receives the clock from the local clock generator 9 supplied to the clock CP, that is, the clock (FIG. 2).
It operates based on the clock shown in d), and the phase synchronization signal 5
The phase is controlled by -1. 8 frequency divided output Q of this counting circuit 19. is shown in FIG. 2(h). Since the counting circuit 19 is set to "111" by the phase synchronization signal 5-1;
Output Q. When the value rises, that is, the count value changes from 11 to 100 after 5 clocks of the local clock. The logic level 1 signal that was in output stage Q when the phase synchronization signal was generated is shifted by five hits to output stage Q. Appears in Therefore, the latch circuit 4 outputs the output Q of the counting circuit 19, which is supplied to the clock input Cp. With the rising edge of , the output stage Q of the shift register 3 is supplied to the data input. Latch the signal. The data input signal and latch output Q signal at this time are shown in Figure 2 (i), U)
(These are shown below. 1. When the sample value at the center position of the multi-point sampled digital signal of logic level 1 is output from the shift register 3, the latch circuit 4 latches it at the latch circuit t'☆4. Therefore, the received signal can be correctly reproduced.

Note that in this embodiment, the output stage Q2 of the shift register 3
The number of logic level 1 among Q- is the output stage Q6-
The phase synchronization signal was output when the number of logic level 1 in Q was equal to or one more than that of logic level 1, but when the former number was equal to or one less than the latter number 1. >' (1) The phase synchronization signal may be output at the time of (1). In this case, the stored input data D, , D2 . By setting the value of D to o, o, o, the same effect as in the previous embodiment can be obtained.

Next, a second embodiment of the present invention will be described using FIG. 4.

In this embodiment, the configuration of the phase control circuit 20 is different from the first embodiment shown in FIG.

The phase control circuit 20 of this embodiment has an adder 21 that adds 1 to the output value 19-1 of the counting circuit 19, and a subtraction 3'? that subtracts the output value 19-1 by 1. - unit 22 and a digital comparator 23 which compares the output value 19-1 of the counting circuit 19 with a constant value.Based on the comparison result of the digital comparator 23, the adder 21. The output value of the subtracter 22 or the output value 19 of the counting circuit 19
-1 and a selector 24 that selects -1 and supplies it to the counting cycle 19 as stored data. Note that the output value 19-
1 is the 8-divided output Q. This includes:

The phase control circuit 1Rr20 counts the phase synchronization signal 5-1[deg.] inputted from the center position detection circuit 5 and supplies it as it is to the storage control input LD of 19. At this time, the digital comparator 23 compares the output value I-1 of the counting circuit 19 with a predetermined value, and if the output value 19-1 is larger, the selector 2
4, the output of the adder 21 is selected; if it is smaller, the output of the subtracter 22 is selected, and if they are the same, the output value 19-1 is selected.

That is, depending on the output value 19-1 when the phase synchronization signal 5-1 is supplied, the counting circuit 19 shifts the phase by one crotter forward or backward, or remains unchanged.

The functional differences between this embodiment and the first embodiment are as follows. In the first embodiment, the counting circuit 19 is set to a constant value I by the phase synchronization signal 5-1, whereas in the present embodiment, the phase changes by at most one clock.

Therefore, in this embodiment, the frequency divided by 8 is the output Q of the counting vessel 19. follows the transmission lock more slowly than in the first embodiment.6 (Effects of the Invention) According to the present invention, the generation of a clock synchronized with the identified digital signal is realized only by the digital circuit. A phase locked circuit suitable for integration can be provided.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG. 2 is a diagram showing a first embodiment of the present invention.
FIG. 3 is a diagram showing the pattern of multi-point sample values that gives the center position of the received signal in this embodiment, and FIG. 4 is a diagram showing the second embodiment of the present invention. It is. In the figure, 1 is a comparator, 2 is a reference voltage source, 3 is a shift register, and 4
is a latch circuit, 5 is a center position detection circuit, 6.7 is a Tekota, 8, 10, 1112, 13, 14, 15, 16°1
7.18 is the gate, 9 is the local clock generator, 19゛
20 is a counting circuit, 20 is a phase control circuit, 21 is an adder 22 is a subtracter, 23 is a digital comparator, and 24 is a selector.

Claims (1)

[Scope of Claims] 1. A local clock generator that generates a local clock with a frequency higher than the transmission frequency, and a system that samples a received transmission code identified as a binary signal using the local clock for one period of the received transmission code. a shift register that stores the above sample values;
A central position where the parallel outputs of this shift register are input and a phase synchronization signal is output upon detecting that the central sample value of the sequence of consecutive discrimination level 1 sample values has reached a predetermined output stage of the shift register. A digital phase synchronization circuit comprising a detection circuit, a counting circuit operated by the local clock, and a phase control circuit controlling the counting operation of the counting circuit based on the phase synchronization signal. 2. The center position detection circuit is configured such that the number of output stages storing sample values of discrimination level 1 is the same or there is a difference between the front and rear output stages with respect to the predetermined output stage of the shift register. 2. The digital phase synchronization circuit according to claim 1, wherein the digital phase synchronization circuit outputs the phase synchronization signal when the phase synchronization signal becomes 1. 3. The digital phase synchronization circuit according to claims 1 and 2, wherein the phase control circuit sets the counting circuit to a predetermined value based on the phase synchronization signal. 4. The phase control circuit compares the count value of the counting circuit when the phase synchronization signal is supplied with a predetermined value;
Claims 1 and 2, characterized in that, when the difference is greater than a certain value, the count value of the counting circuit is shifted forward or backward by a certain value depending on the sign of the difference. digital phase-locked circuit.