JPH08111070A - Reproducing device - Google Patents

Abstract

PURPOSE: To improve stability of a regenerative clock and to eliminate an identification timing error due to circuit delay difference. CONSTITUTION: Signals regenerated by rotary heads 2a, 2b are amplified by reproducing amplifiers 3a, 3b respectively, and a prescribed signal processing are performed by detection circuits 5a, 5b, and they are data-strobed by latch circuits 8a, 8b. Further, bit clock components extracted by clock component extraction circuits 11a, 11b are phase-compared with an output signal of a VCO 15 and the signal delaying it by a delay device 21 by phase comparators 12a, 12b respectively, and these phase error signals are added by an adder 13 to be fed back to the VCO 15 through an LPF 14. Then, the output signal of the VCO 15 and the signal delaying it by the delay device 21 are supplied to the latch circuits 8a, 8b through the delay devices 22, 23 as strobe clocks respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus for digital information signals, and more particularly to a reproducing apparatus suitable for reproducing two tracks by two adjacent rotary heads.

[0002]

2. Description of the Related Art An apparatus for reproducing two tracks by using two adjacent rotary heads, a so-called double azimuth head, is described in, for example, JP-A-4-6674. This generates a first clock synchronized with the reproduction signal of one rotary head and delays the first clock by a predetermined amount to obtain a second clock synchronized with the reproduction signal of the other rotary head. It is the one.

[0003]

However, in the above-mentioned prior art, only the reproduction signal of one of the rotary heads is supplied to the PLL circuit for generating the clock,
No consideration was given to improving the stability of the reproduction clock by supplying the reproduction signals of both rotary heads.

Further, no consideration has been given to the identification timing error caused by the delay difference between the reproduction detection circuit for detecting digital information from the reproduction signal and the PLL circuit.

The object of the present invention is to solve the above-mentioned drawbacks of the prior art and to improve the stability of the reproduced clock.
An object of the present invention is to provide a reproducing device that eliminates an identification timing error.

[0006]

In order to achieve the above object, according to the present invention, first and second clock component extracting means for extracting clock components from reproduced signals of both rotary heads, and voltage controlled oscillating means. First delay means for delaying the output signal of the voltage controlled oscillation means, and first phase comparison means for comparing the phases of the output signals of the first clock component extraction means and the output signal of the voltage controlled oscillation means, Second phase comparison means for comparing the phases of the output signals of the second clock component extraction means and the output signals of the first delay means, and the output signals of the first and second phase comparison means are added to perform voltage-controlled oscillation. It comprises an adding means for controlling the output frequency of the means, a second delay means for delaying the output signal of the voltage controlled oscillation means, and a third delay means for delaying the output signal of the first delay means.

The output signals of the second and third delay means are used as the first and second clocks, respectively, to identify the recorded digital information from the reproduced signals of both rotary heads.

[0008]

Since the output frequency of the voltage controlled oscillator is controlled by the phase error signal of the clock component extracted from the reproduction signals of both rotary heads, the gain of the PLL loop increases, and as a result, the phase pull-in range increases. It is possible to improve stability after synchronization.

The delay time difference between the reproduction signals of both rotary heads is compensated by the first delay means, and the reproduction detection circuit and P
The error in the identification timing caused by the delay difference of the LL circuit is compensated by the second and third delay means.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a reproducing apparatus according to the present invention. Here, 1 is a magnetic tape, 2
a, 2b are rotary heads, 3a, 3b are reproduction amplifiers, 5
a, 5b are detection circuits, 8a, 8b are latch circuits, 9a,
9b is an output terminal, 11a and 11b are clock component extraction circuits, 12a and 12b are phase comparators, 13 is an adder, and 14
Is a low pass filter (LPF), 15 is a voltage controlled oscillator (V
CO), 21, 22 and 23 are delay devices. Incidentally, the rotary heads 2a and 2b have a step of one track pitch in the height direction on the rotary drum (not shown) as in the conventional case, and are integrally fixed by being displaced forward and backward with respect to the rotational direction. The digital information signals recorded on the diagonal tracks of the magnetic tape 1 are sequentially reproduced.

The reproduction signals reproduced by the rotary heads 2a and 2b and amplified to appropriate levels by the reproduction amplifiers 3a and 3b are subjected to predetermined signal processing by the detection circuits 5a and 5b, respectively, and latch circuits 8a and 8b. Is supplied to. The latch circuits 8a and 8b respectively strobe data on the basis of the input clock and output the obtained digital information signals via the output terminals 9a and 9b.

The reproduced signals of the two systems are also supplied to the clock component extraction circuits 11a and 11b, and the bit clock component of the recorded digital information signal is extracted. The phase comparator 12a compares the phase of the bit clock component extracted by the clock component extraction circuit 11a with the output signal of the VCO 15, and outputs the phase error signal. Similarly, the phase comparator 12b delays the bit clock component extracted by the clock component extraction circuit 11b and the V delayed by the delay unit 21.
The output signals of the CO 15 are compared in phase and the phase error signal is output. These phase error signals are added by the adder 13 and fed back to the VCO 15 via the LPF 14. At this time, the delay time of the delay device 21 is set so as to compensate for the clock phase difference due to the delay time difference between the reproduction signals of the rotary heads 2a and 2b, as in the conventional case.

As described above, since the output frequency of the VCO 15 is controlled by the phase error signal of the clock component extracted from the reproduction signals of both rotary heads 2a and 2b, the PLL.
The loop gain increases, and as a result, the phase pull-in range can be increased and the stability after synchronization can be improved.

On the other hand, the delay devices 22 and 23 respectively include the detection circuits 5a and 5b and the clock component extraction circuits 11a and 11 respectively.
These delay times are set so as to compensate for the clock phase difference due to the delay difference of b, and their output signals are supplied to the latch circuits 8a and 8b as strobe clocks. As a result, even in the case of high-density recording in which the recording bit rate is high and the delay difference between the detection circuit and the PLL circuit cannot be ignored, the identification timing can be kept good.

FIG. 2 is a block diagram showing another embodiment of the reproducing apparatus according to the present invention. This embodiment is an application example to a system using the partial response class IV (PR4) detection method. Here, 4a and 4b are equalization circuits, and 6
a and 6b are (1 + D) circuits, 7a and 7b are ternary comparators, 16a and 16b are quadratic circuits, 31, 32 and 33 are variable delay devices, and 41 and 42 are phase error detection circuits. The same reference numerals as in FIG.

The signals reproduced by the rotary heads 2a and 2b are amplified to appropriate levels by the reproduction amplifiers 3a and 3b, respectively, so that the impulse responses become (1, -1) in the equalization circuits 4a and 4b. Are equalized. The (1 + D) circuits 6a and 6b include 1-bit delay devices 61a and 61b, respectively.
b and adders 62a and 62b, the equalized signal is further converted into an impulse response of (1, 0, -1), that is, a PR4 signal. Three-value comparator 7a, 7b
Converts a ternary PR4 signal at a predetermined threshold level and converts it into a binary signal. Then, the latch circuits 8a and 8b respectively strobe the data based on the input clock, and output the obtained digital information signal via the output terminals 9a and 9b.

The equalized two-system reproduced signals are also supplied to the fourth power circuits 16a and 16b, and the bit clock component of the recorded digital information signal is extracted. This 4
The multiplication circuits 16a and 16b are the clock component extraction circuit 1 of FIG.
Needless to say, it corresponds to 1a and 11b. The phase comparator 12a compares the phase of the bit clock component extracted by the quadratic circuit 16a with the output signal of the VCO 15, and outputs the phase error signal. Similarly, the phase comparator 12b
Outputs the phase error signal by comparing the phase of the bit clock component extracted by the quadratic circuit 16b with the output signal of the VCO 15 delayed by the variable delay unit 31. And
These phase error signals are added by the adder 13 and the LPF is added.
It is returned to the VCO 15 via 14. As described above, in this embodiment as well, as in the embodiment of FIG. 1, the output frequency of the VCO 15 is controlled by the phase error signal of the clock component extracted from the reproduced signals of both rotary heads 2a and 2b, so that the reproduced clock is generated. The stability of can be improved.

Another feature of this embodiment is that the delay units 21, 22, 23 in FIG. 1 are replaced by variable delay units 31, 32, 3.
3, and these are configured to be controlled by the phase error detection circuits 41 and 42. This operation will be described below.

The variable delay unit 31 includes rotary heads 2a, 2
It is for compensating for the clock phase difference due to the delay time difference of the reproduction signal of b, and the variable delay devices 32 and 33 are (1 + D) circuits 6a and 6b and ternary comparators 7a and 7b and quadratic circuit 16a, respectively. The purpose of compensating for the clock phase difference caused by the delay difference of 16b is as follows.
This is similar to the embodiment of FIG.

The phase error detection circuits 41 and 42 detect the phase error between the data and the clock input to the latch circuits 8a and 8b, respectively. The phase error detected by the phase error detection circuit 41 is the (1 + D) circuits 6a and 3
The clock phase difference due to the delay difference between the value comparator 7a and the quadratic circuit 16a is shown. Therefore, by controlling the variable delay device 32 with this phase error signal, automatic correction is performed. (1 + D) circuit 6b and ternary comparator 7b
The clock phase difference resulting from the delay difference between the fourth power circuit 16b and the fourth power circuit 16b is basically equal to the clock phase difference resulting from the delay difference between the (1 + D) circuit 6a and the ternary comparator 7a and the fourth power circuit 16a. 33 may be controlled by the phase error signal detected by the phase error detection circuit 41, similarly to the variable delay device 32. Therefore, the remaining rotary heads 2a, 2
The clock phase difference due to the delay time difference of the reproduced signal of b is detected by the phase error detection circuit 42, and the variable delay device 31 may be controlled by this phase error signal.

As described above, in the present embodiment, all the clock phase differences due to the delay difference due to the rotary head and the circuit delay difference can be automatically corrected, so that it is possible to cope with the drift due to the passage of time or environmental changes.

[0023]

As described above, according to the present invention, the stability of the reproduced clock can be improved, and even in the case of a high recording bit rate where the delay difference between the detection circuit and the PLL circuit cannot be ignored. Since the identification timing can be kept good, high density recording can be realized as a result.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a reproducing apparatus according to the present invention.

FIG. 2 is a block diagram showing another embodiment of the reproducing apparatus according to the present invention.

[Explanation of symbols]

 2a, 2b ... Rotary head, 4a, 4b ... Equalization circuit, 5a, 5b ... Detection circuit, 6a, 6b ... (1 + D) circuit, 7a, 7b ... Tri-level comparator, 8a, 8b ... Latch circuit, 11a, 11b ... Clock component extraction circuit, 12a, 12b ... Phase comparator, 13 ... Adder, 14 ... Low-pass filter (LPF), 15 ... Voltage controlled oscillator (VCO), 16a, 16b ... Quadrature circuit, 21, 22, 23 ... Delay device, 31, 32, 33 ... Variable delay device, 41, 42 ... Phase error detection circuit.

Claims (4)

[Claims] 1. A first and a second rotary head, which have a step difference of 1 track pitch in the height direction and are integrally fixed by being shifted forward and backward with respect to the rotation direction, are sequentially formed in an oblique direction of a recording medium. In an apparatus for reproducing a digital information signal recorded on a formed track, a first detecting means for detecting the recorded digital information signal from the first and second reproduction signals reproduced by the first and second rotary heads, respectively. First and second detecting means, first and second identifying means for identifying the output signals of the first and second detecting means based on the first and second clocks, respectively, and the first and second detecting means. First and second clock component extracting means for respectively extracting the clock components of the recorded digital information signal from the reproduced signal, the voltage control oscillation means, and the output signal of the voltage control oscillation means delayed. Delaying means, first phase comparing means for comparing the phases of the output signal of the first clock component extracting means and the output signal of the voltage controlled oscillating means, and the output signal of the second clock component extracting means. Second phase comparison means for comparing the phases of the output signals of the delay means and addition means for adding the output signals of the first and second phase comparison means and controlling the output frequency of the voltage controlled oscillation means. The output signals of the voltage controlled oscillating means and the delay means are respectively used as the first and second clocks, and the delay time of the delay means is made equal to the delay time difference between the first and second reproduction signals. Characterizing playback device. 2. The first signal according to claim 1, wherein the output signal of the voltage controlled oscillator is delayed.
Second delay means for compensating the delay time difference between the output signal of the detection means and the output signal of the voltage controlled oscillation means, and the output signal of the second detection means and the delay signal for delaying the output signal of the delay means. A third delay means for compensating for a delay time difference between the output signals of the means, and the output signals of the second and third delay means being the first and second clocks, respectively. . 3. A first and a second rotary head, which have a step difference of 1 track pitch in the height direction and are fixed to each other by being shifted forward and backward with respect to the rotation direction, are sequentially formed in an oblique direction of a recording medium. In an apparatus for reproducing a digital information signal recorded on a formed track, a first detecting means for detecting the recorded digital information signal from the first and second reproduction signals reproduced by the first and second rotary heads, respectively. First and second detecting means, first and second identifying means for identifying the output signals of the first and second detecting means based on the first and second clocks, respectively, and the first and second detecting means. First and second clock component extracting means for respectively extracting the clock components of the recorded digital information signal from the reproduced signal, the voltage control oscillation means, and the output signal of the voltage control oscillation means delayed. First variable delay means, first phase comparing means for comparing the phases of the output signals of the first clock component extracting means and the output signals of the voltage controlled oscillating means, and the second clock component extracting means. Output signal of the first variable delay means and second phase comparison means for comparing the output signal of the first variable delay means with the output signals of the first and second phase comparison means, and the output of the voltage controlled oscillation means. An addition means for controlling the frequency; a second variable delay means for delaying an output signal of the voltage controlled oscillation means and using the output signal as the first clock; and an output signal of the first variable delay means. A third variable delay means that delays the output signal to be the second clock; a phase error between the output signal of the first detection means and the first clock is detected; A first phase for controlling the second and third variable delay means Error detecting means, and second phase error detecting means for detecting a phase error between the output signal of the second detecting means and the second clock and controlling the first variable delay means with the output signal. A reproducing device characterized by being provided. 4. The method according to claim 3, wherein the first and second detecting means are partial response class IV detecting means, and the first and second clock component extracting means are respectively quadratic means. A reproducing apparatus characterized in that.