JPH10283737A - Digital phase control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital phase control circuit for preventing deviation from phase synchronization for such jitter as a peak shift. SOLUTION: A phase detection circuit 12 detects a phase difference between an input signal 103 and an output signal 108 including a direction, and a peak shift detection circuit 13 judges whether a phase difference being detected by the phase detection circuit 12 exceeds a specific value or not. When it judges that the detected phase difference does not exceed the specific value, a phase difference direction detection circuit 14 increases or decreases its output value based on the direction of the phase difference, a specific range excess detection circuit 15 judges whether the output of the phase difference direction detection circuit 14 exceeds a specific range or not. Then, when the output of the phase difference direction detection circuit 14 exceeds a specific range, a binary counter 16 controls the phase of the output signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital phase control circuit, and more particularly to a digital phase control circuit used for a floppy disk drive.

[0002]

2. Description of the Related Art Generally, data recording on a floppy disk is performed by an FM (Frequency Modulation) system or an MFM (Modified Frequency Modulation) system. And data bits.

Therefore, when reading data from a floppy disk, a clock synchronized with the reproduced data is required to separate the clock bits from the data bits. FIG. 4 shows a configuration example of a conventional digital phase control circuit for generating a clock synchronized with the reproduced data.

In FIG. 4, reproduced data 301 output from a floppy disk drive is normalized by a reference circuit 31 via a reference clock 302. The scaled reproduction data (hereinafter, also referred to as scaled data) 303 output from the scaling circuit 301 is input to the binary counter 32. The binary counter 32 has a reset function and outputs a signal 304. Further, the MSB indicated in the binary counter 32 represents the most significant bit. The toggle flip-flop 33 has a function as a divide-by-2 circuit, and outputs an output clock 305.

Here, for simplicity of explanation, the reproduction data 301 is of the above-mentioned MFM system, and the transfer speed is 50
0 Kbps, and the binary counter 32 has a 4-bit configuration. In this case, the output clock 305 is set to 50
The reference clock 302 may be set to 16 MHz in order to set it to 500 KHz corresponding to the transfer rate of 0 Kbps. Further, it is assumed that the case where the normalized reproduction data 303 is located at the center of the “high” or “low” period of the output clock 305 has an ideal phase relationship.

Next, FIGS. 5 and 6 show timing charts of output signals of respective blocks of the digital phase control circuit shown in FIG. Here, the timing chart shown in FIG. 5A shows the relationship between the output clock 305 when the reproduction data 301 is not input and the count output value 304 of the binary counter 32. According to FIG. 5A, the above-described ideal phase relationship is defined by the reference data 30
It can be seen that 3 is the case where the count output value 304 of the binary counter 32 is at the position of 0.

Therefore, the reference data 30 shown in FIG.
If the binary counter 32 is configured to be reset according to 3, the ideal phase relationship can be maintained.

On the other hand, FIG. 5B shows an output clock 305, reference data 303, and a count output value 304 of the binary counter 32 in the case of the ideal phase relationship described above.
FIG. In FIG. 5B, the standardized data 303 is configured by a pattern of 10101 °. The bit interval between two consecutive reference data 303 is set to 2 μsec corresponding to 32 clocks of the reference clock 302, and the fluctuation of reproduced data such as jitter is extremely small.

[0009]

However, in the above-described conventional digital phase control circuit, the phase control is performed immediately after the reproduction data is input. Therefore, one of the features of the reproduction data output from the floppy disk drive is one. When two consecutive data have phase shifts opposite to each other, such as data having a peak shift, there is a problem that the phase shift is likely to be out of phase synchronization.

For example, FIG. 6 shows a timing chart when the above-mentioned synchronization is lost. In this case, the pattern of the input data is 10001010001 °, and the bits on both sides of the portion 101 are out of phase with each other due to the peak shift. The dotted line shows an example where there is no peak shift.

When such a loss of synchronization occurs, the reliability of the operation of the digital phase control circuit decreases.

The present invention has been made in view of the above circumstances,
An object of the present invention is to provide a highly reliable digital phase control circuit for a digital phase control circuit used in a floppy disk drive by preventing loss of phase synchronization with respect to jitter such as peak shift. .

[0013]

According to the first aspect of the present invention,
In a digital phase control circuit that outputs an output signal having a predetermined phase relationship with an input signal, detecting means for detecting a phase difference between the input signal and the output signal including its direction, and detecting the phase difference. Determining means for determining whether or not the phase difference exceeds a predetermined value; and determining that the detected phase difference does not exceed the predetermined value by the determination of the determining means. Counting means for increasing or decreasing the output value based on the direction of; an excess detection means for determining whether or not the output value of the counting means is outside a predetermined range; and And a phase control means for controlling the phase of the output signal when it is determined that the output value exceeds the predetermined range.

Therefore, according to the present invention, when the read data is input, the phase of the final output is not immediately corrected, but it is determined whether or not the phase difference exceeds a predetermined value. The output value of the counting means is increased or decreased based on the determination result, and it is further determined whether or not this output value is within a predetermined range. Therefore, the deviation from the phase synchronization with respect to jitter such as peak shift is reduced. can do.

According to a second aspect of the present invention, in the first aspect of the present invention, the digital phase control circuit detects a SYNC pattern in the input signal. It has a SYNC pattern detecting means for outputting a detection signal.

Therefore, according to the present invention, the operation of the invention described in claim 1 can be obtained, and the SYNC section performs high-speed phase synchronization, and the ID section and the data section receive data having a peak shift. Is also hard to deviate from the synchronization, so that finer phase synchronization can be performed.

[0017]

Next, an embodiment of a digital phase control circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a digital phase control circuit according to the present invention. As shown in FIG. 1, the digital phase control circuit according to the present embodiment includes a reference circuit 11, a phase difference detection circuit 12, a peak shift detection circuit 13, and a phase difference direction detection circuit 14.
A predetermined range excess detection circuit 15 and a binary counter 16
And a toggle flip-flop 17.

Next, the operation of the digital phase control circuit will be described. In FIG. 1, reproduction data 101 output from a floppy disk drive is input to a standardization circuit 11. The reference clock 1 is supplied to the reference circuit 11.
02 is also input, and if a clock bit or data bit exists in the reproduction data 101, the pulse width is synchronized with the reference clock 102 and the pulse width thereof is
The reference data 103 corresponding to two cycles is output.

The phase difference detection circuit 12 outputs the reference data 10
3 and the binary counter value 1 output from the binary counter 16
08, and outputs a phase difference value 104 indicating how many cycles of the reference clock 102 the position of the reference data 103 is shifted from a position having an ideal phase relationship with the output clock 108. The sign of the phase difference value 104 can be used to determine whether the shift is temporally earlier or later.

The peak shift detecting circuit 13 receives the phase difference value 104 and determines whether or not the value exceeds a predetermined range, that is, whether or not the data has a peak shift. If it is determined that the data has a shift, a signal 105 for instructing the phase difference direction detection circuit 14 to stop counting is output.

Further, the phase difference direction detection circuit 14 inputs the reference data 103, the phase difference value 104, and a signal 105 for instructing stop of counting. At this time, when the stop of the count is not instructed by the signal 105 for instructing the stop of the count and the reference data 103 is present, the output value 106 is increased or decreased according to the sign of the phase difference value 104. .

The predetermined range excess detection circuit 15 receives the output value 106 of the phase difference direction detection circuit 14 and outputs a signal 107 indicating whether the value has exceeded a predetermined range. However, the predetermined range excess detection circuit 15 outputs the detection signal 107 when the difference between the number of times when the phase shift direction is earlier in time and the number of times when the phase shift direction is later exceeds a predetermined range.

The binary counter 16 and the toggle flip
The operation of the flop 17 is the same as in the conventional example. Therefore, when the scaled data 103 is input, the peak shift is not detected by the peak shift detection circuit 13, and the output value of the phase direction detection circuit 14 exceeds the predetermined range excess detection circuit 15.
When it is detected that the data exceeds the predetermined range, the reference data 103 is located in the ideal phase relationship with the output clock 109, that is, at the center of the “high” or “low” period of the output clock 109. Will be. At this time, the output value 108 of the binary counter 16 is 0.

From the above description, according to the present embodiment, the predetermined range of the peak shift detection circuit 13 is set to be sufficiently large so that the peak shift is not detected, and the predetermined range of the predetermined range excess detection circuit 15 is set to -1. If the reproduction data includes a clock bit or a data bit, the binary counter 16 is reset every time, and the operation is exactly the same as that of the conventional example.

Here, for comparison with the conventional example, the operation, numerical values and the like of each block will be specifically defined. First, the transfer rate of the reproduced data is 500Kbp by MFM method.
s, and the frequency of the reference clock 102 is 16 MHz. If the phase difference value 104 is a negative value, the direction of the phase shift is the direction of the phase advance, and if the phase difference value is a positive value, the direction of the phase delay is the direction of the phase delay.

When the value of the phase difference value 104 exceeds the range of -4 to +4, the peak shift detection circuit 13 detects the value and outputs a signal 105 for instructing the phase difference direction detection circuit 14 to stop counting. The phase difference direction detection circuit 14 is configured to be an up / down counter configured to increase when the phase difference value 104 is a positive value and decrease when the phase difference value 104 is a negative value. When the output value 106 of the phase difference direction detection circuit 14 exceeds the range of −2 to +2, the circuit 15 detects this and outputs a reset signal 107 to the binary counter 16.

FIG. 2 shows a timing chart of the output clock 109 and the reference data 103 described above. In this figure, the numbers entered are the reference clock 102
Shows the time length based on the number of clocks.
The time between two data bits is 32 clocks of the reference clock 102, as in the case shown in FIG.

As shown in FIG. 2, since the left data bit has a phase difference value of -5, the peak shift detecting circuit 13 detects the peak shift, and the phase difference direction detecting circuit 14 On the other hand, a signal 10 for instructing stop of counting
5 is output. Therefore, the predetermined range excess detection circuit 15 does not output the reset signal 102 to the binary counter 16, and the cycle of the output clock 109 is 32 clocks of the reference clock 102, as in the case where there is no peak shift. .

Therefore, as is apparent from FIG.
Even if data having a peak shift is input, there is no deviation from phase synchronization.

Next, a digital phase control circuit according to a second embodiment of the present invention will be described with reference to the drawings.
FIG. 3 shows a block diagram of a digital phase control circuit according to a second embodiment of the present invention.

The configuration of the second embodiment is different from the configuration of the first embodiment in that the SYNC pattern detection circuit 28 to which the reference data 203 and the output signal 209 from the toggle flip-flop 27 are input. And the output of the SYNC pattern detection signal 210 is input to the predetermined range excess detection circuit 25.

Here, the SYNC pattern is a SYNC pattern added immediately before the ID part and the data part in the output data string output from the floppy disk drive.
The data pattern of the portion C has a pattern of 101010 °. The SYNC pattern detection circuit 28 detects this pattern, and outputs a SYNC pattern detection signal 210 to the predetermined range excess detection circuit 25 after detecting this pattern by a predetermined number of bits. .

In the SYNC pattern, since the magnetic interference is uniform for each bit, almost no jitter or peak shift occurs. Therefore, the phase shift in this pattern is only the initial phase difference, and even if the same phase correction as in the conventional example is performed, synchronization is not lost, so that high-speed phase synchronization can be performed.

The operation of the other blocks is the same as the operation of the blocks in the first embodiment, and will not be described.

Therefore, according to the second embodiment, S
Until the detection signal 210 is output for the YNC pattern,
Since the predetermined range of the predetermined range excess detection circuit 25 is set to −1 to +1, if the SYNC pattern detection signal 210 is output, if the predetermined range is set to −2 to +2, S
Digital phase control capable of performing high-speed phase synchronization in the YNC section, and performing finer phase synchronization such that the ID section and the data section are unlikely to lose synchronization even when data having a peak shift is input. A circuit can be provided.

[0037]

As is apparent from the above description, according to the present invention, the phase correction is directly performed on the data having the peak shift and the data having the smaller phase shift by the phase difference. Instead of performing the phase correction after determining whether or not the phase difference is within a predetermined range, it is possible to prevent deviation from phase synchronization. Therefore, it is possible to provide a digital phase control circuit capable of reducing the read error rate for the floppy disk device.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a digital phase control circuit according to the present invention.

FIG. 2 is a timing chart of main signals in the digital phase control circuit shown in FIG.

FIG. 3 is a block diagram of a digital phase control circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a conventional digital phase control circuit.

FIG. 5 is a timing chart of main signals in a conventional digital phase control circuit.

FIG. 6 is a timing chart of main signals in a conventional digital phase control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Standardization circuit 12 Phase difference detection circuit 13 Peak shift detection circuit 14 Phase difference direction detection circuit 15 Predetermined range excess detection circuit 16 Binary counter 17 Toggle flip-flop 21 Standardization circuit 22 Phase difference detection circuit 23 Peak shift detection circuit 24 Phase difference direction detection circuit 25 Predetermined range excess detection circuit 26 Binary counter 27 Toggle flip-flop 28 SYNC pattern detection circuit

Claims (2)

[Claims] 1. A digital phase control circuit for outputting an output signal having a predetermined phase relationship with an input signal, comprising: a detecting means for detecting a phase difference between the input signal and the output signal including a direction thereof; Determining means for determining whether the phase difference detected by the means exceeds a predetermined value; and determining that the detected phase difference does not exceed a predetermined value by the determination of the determining means. Counting means for increasing or decreasing the output value based on the direction of the phase difference; excess detection means for determining whether the output value of the counting means exceeds a predetermined range; and determination by the excess detection means. A phase control means for controlling the phase of the output signal when it is determined that the output value of the counting means exceeds a predetermined range. 2. The digital phase control circuit detects a SYNC pattern in the input signal.
2. The digital phase control circuit according to claim 1, further comprising: a SYNC pattern detecting means for outputting a detection signal to said excess detecting means when a YNC pattern is detected.