JPS56169296A - Compensation system for memory destruction - Google Patents

Compensation system for memory destruction

Info

Publication number
JPS56169296A
JPS56169296A JP7334280A JP7334280A JPS56169296A JP S56169296 A JPS56169296 A JP S56169296A JP 7334280 A JP7334280 A JP 7334280A JP 7334280 A JP7334280 A JP 7334280A JP S56169296 A JPS56169296 A JP S56169296A
Authority
JP
Japan
Prior art keywords
order
signals
destruction
elements
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7334280A
Other languages
Japanese (ja)
Inventor
Yuji Nakagawa
Akira Yasuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP7334280A priority Critical patent/JPS56169296A/en
Publication of JPS56169296A publication Critical patent/JPS56169296A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Abstract

PURPOSE:To compensate for destruction rapidly by changing an order signal which accesses memory elements in a memory block successively, through a switch circuit according to a destruction signal from a high-order element. CONSTITUTION:When the high-order two bits, etc., of the common address of memory elements M1... constituting a memory block M are applied to a decoding circuit D, chip enable signals are applied as order signals via a decoder D1 and a switch part S in the order of high-order elements M1, M2... to attain access in the order of thehigh-order elements M1.... On the other hand, if destruction signals are applied from the high-order elements M1... via a control part, the order of the order signals is changed via the switch part S according to the destruction signals. This system which changes the order of the order signals without arithmetic, etc., speeds and secure destruction compensation.
JP7334280A 1980-05-31 1980-05-31 Compensation system for memory destruction Pending JPS56169296A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7334280A JPS56169296A (en) 1980-05-31 1980-05-31 Compensation system for memory destruction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7334280A JPS56169296A (en) 1980-05-31 1980-05-31 Compensation system for memory destruction

Publications (1)

Publication Number Publication Date
JPS56169296A true JPS56169296A (en) 1981-12-25

Family

ID=13515381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7334280A Pending JPS56169296A (en) 1980-05-31 1980-05-31 Compensation system for memory destruction

Country Status (1)

Country Link
JP (1) JPS56169296A (en)

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