JPS56165417A - Code transmitting circuit - Google Patents

Code transmitting circuit

Info

Publication number
JPS56165417A
JPS56165417A JP6874980A JP6874980A JPS56165417A JP S56165417 A JPS56165417 A JP S56165417A JP 6874980 A JP6874980 A JP 6874980A JP 6874980 A JP6874980 A JP 6874980A JP S56165417 A JPS56165417 A JP S56165417A
Authority
JP
Japan
Prior art keywords
code
phi
multiplexer
supplied
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6874980A
Other languages
Japanese (ja)
Inventor
Jiro Mizukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP6874980A priority Critical patent/JPS56165417A/en
Publication of JPS56165417A publication Critical patent/JPS56165417A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

Abstract

PURPOSE:To realize a conversion from a parallel code into a series code through a simple constitution, by counting the reference pulse having a cycle corresponding to the transmitting speed of the series code and then supplying the output of count to a multiplexer as a channel selection signal. CONSTITUTION:When the reference pulse is supplied, the signals phi.2<0>-phi.2<5> are delivered from output terminals QA-QD of the binary 16-notation counters 1 and 2. Then each bit signal of the parallel code PD supplied to the multipleer channels CH0-CH15 of a multiplexer 3 is selected successively and then delivered from an output terminal OUT. The all-mark code with its all bits set at the H level is transmitted in the form of a series code SD in a section during which the output signal phi.2<5> of the counter 2 is set at the L level. The output signal of the multiplexer 3 is not reversed in the first half part of a section during which the signal phi.2<5> is set at the H level and then reversed at the second half part by an exclusive OR gate 4 to be supplied to a NAND gate 5.
JP6874980A 1980-05-23 1980-05-23 Code transmitting circuit Pending JPS56165417A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6874980A JPS56165417A (en) 1980-05-23 1980-05-23 Code transmitting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6874980A JPS56165417A (en) 1980-05-23 1980-05-23 Code transmitting circuit

Publications (1)

Publication Number Publication Date
JPS56165417A true JPS56165417A (en) 1981-12-19

Family

ID=13382722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6874980A Pending JPS56165417A (en) 1980-05-23 1980-05-23 Code transmitting circuit

Country Status (1)

Country Link
JP (1) JPS56165417A (en)

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