JPS56137755A - Parallel-series converting circuit - Google Patents

Parallel-series converting circuit

Info

Publication number
JPS56137755A
JPS56137755A JP4081780A JP4081780A JPS56137755A JP S56137755 A JPS56137755 A JP S56137755A JP 4081780 A JP4081780 A JP 4081780A JP 4081780 A JP4081780 A JP 4081780A JP S56137755 A JPS56137755 A JP S56137755A
Authority
JP
Japan
Prior art keywords
parallel
transmitted
bit counter
inputted
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4081780A
Other languages
Japanese (ja)
Inventor
Hiroichi Naganawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4081780A priority Critical patent/JPS56137755A/en
Publication of JPS56137755A publication Critical patent/JPS56137755A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/45—Transmitting circuits; Receiving circuits using electronic distributors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Electronic Switches (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To simplify the constitution of a parallel-series converting circuit by using pulses having time width matching with the transmission speed of codes and a counting circuit which is driven with the pulses. CONSTITUTION:Once start signal S arrives, starting circuit 12 operates to open AND gate 15 and transmitted-bit counter 17 is driven with pulse P having cycles equal to the time width of one bit; and its output is converted by decoder 18 into a decimal number, and its outputs 1-(n) and parallel inputs I1-In are inputted to AND gates A11-A1n respectively. Each AND gate output is inputted to OR gate OR. Once transmitted-bit counter 17 is driven with pulse P, its outputs are inputted to corresponding AND gates A11-A1n and parallel input signals I1-In are outputted as series output signals successively by one pulse P at a time. When transmitted-bit counter 17 counts up to n+1, driving circuit 12 and transmitted-bit counter 17 are reset with this parallel-series conversion end signal.
JP4081780A 1980-03-29 1980-03-29 Parallel-series converting circuit Pending JPS56137755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4081780A JPS56137755A (en) 1980-03-29 1980-03-29 Parallel-series converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4081780A JPS56137755A (en) 1980-03-29 1980-03-29 Parallel-series converting circuit

Publications (1)

Publication Number Publication Date
JPS56137755A true JPS56137755A (en) 1981-10-27

Family

ID=12591199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4081780A Pending JPS56137755A (en) 1980-03-29 1980-03-29 Parallel-series converting circuit

Country Status (1)

Country Link
JP (1) JPS56137755A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083415A (en) * 1983-10-14 1985-05-11 Sony Corp Variable delay circuit
JPS6489746A (en) * 1987-09-30 1989-04-04 Fujitsu Ltd Serial/parallel converter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083415A (en) * 1983-10-14 1985-05-11 Sony Corp Variable delay circuit
JPS6489746A (en) * 1987-09-30 1989-04-04 Fujitsu Ltd Serial/parallel converter
JPH0524698B2 (en) * 1987-09-30 1993-04-08 Fujitsu Ltd

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