JPS5797233A - Multichannel pulse counting system - Google Patents

Multichannel pulse counting system

Info

Publication number
JPS5797233A
JPS5797233A JP17263780A JP17263780A JPS5797233A JP S5797233 A JPS5797233 A JP S5797233A JP 17263780 A JP17263780 A JP 17263780A JP 17263780 A JP17263780 A JP 17263780A JP S5797233 A JPS5797233 A JP S5797233A
Authority
JP
Japan
Prior art keywords
signal
channel
subtraction
signals
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17263780A
Other languages
Japanese (ja)
Inventor
Chika Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP17263780A priority Critical patent/JPS5797233A/en
Publication of JPS5797233A publication Critical patent/JPS5797233A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers

Landscapes

  • Radar Systems Or Details Thereof (AREA)

Abstract

PURPOSE:To achieve pulse counting of multi-channel with simple circuit constitution, by determining addition or subtraction of input pulses through the combination of an input signal at present sample with an input signal at the previous sample. CONSTITUTION:A status memory 11 transmits channel status signals A1i, B1i and A2i, B2i at the present and previous points of time to a channel switching circuit, in synchronizing with a sample clock CK1. A channel switching circuit 12 selects one channel with a switching signal D. A selected status signal is an address input of an ROM13 together with double frequency switching signals C1, C2, and an output of the ROM13 is outputted as an addition signal PU and a subtraction signal PD through the combination of the signals. A count circuit 14 adds or subtracts a count clock CK2 with the addition signal PU or the subtraction signal PD.
JP17263780A 1980-12-09 1980-12-09 Multichannel pulse counting system Pending JPS5797233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17263780A JPS5797233A (en) 1980-12-09 1980-12-09 Multichannel pulse counting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17263780A JPS5797233A (en) 1980-12-09 1980-12-09 Multichannel pulse counting system

Publications (1)

Publication Number Publication Date
JPS5797233A true JPS5797233A (en) 1982-06-16

Family

ID=15945564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17263780A Pending JPS5797233A (en) 1980-12-09 1980-12-09 Multichannel pulse counting system

Country Status (1)

Country Link
JP (1) JPS5797233A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53119660A (en) * 1977-03-29 1978-10-19 Sharp Corp Signal scaler
JPS5437675A (en) * 1977-08-31 1979-03-20 Toshiba Corp Pulse count circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53119660A (en) * 1977-03-29 1978-10-19 Sharp Corp Signal scaler
JPS5437675A (en) * 1977-08-31 1979-03-20 Toshiba Corp Pulse count circuit

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