JPS56164646A - Monitor signal transmitting device - Google Patents

Monitor signal transmitting device

Info

Publication number
JPS56164646A
JPS56164646A JP6776880A JP6776880A JPS56164646A JP S56164646 A JPS56164646 A JP S56164646A JP 6776880 A JP6776880 A JP 6776880A JP 6776880 A JP6776880 A JP 6776880A JP S56164646 A JPS56164646 A JP S56164646A
Authority
JP
Japan
Prior art keywords
write
address
bit
signal
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6776880A
Other languages
Japanese (ja)
Inventor
Makoto Mori
Shiro Kikuchi
Masaki Ehata
Susumu Shirasawa
Shuzo Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP6776880A priority Critical patent/JPS56164646A/en
Publication of JPS56164646A publication Critical patent/JPS56164646A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/14—Monitoring arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To quickly write the status of line as a digital monitor signal, by providing the high-order address latch circuit to write the digital monitoring signal in a transmission storage memory, low-order address generating circuit and a 16-bit latch circuit. CONSTITUTION:A processor 14 sets the status of lines, the 1st instruction outputs the high-order address of a transmission storage memory 11 and the 2nd instruction outputs the digital monitor signal (SS signal bit) for 16 lines' share, in the number of bits possible for simultaneous output, e.g., in 16 bits, by the control bus. Next, the low-order, address of the memory 11 is produced from a 16-notation counter 22 to constitute the write-in address together with the high-order address stored in a circuit 21, and an SS signal bit corresponding to this address is written in the memory 11 through a 1/16 selector 24 from a data latch circuit 23 sequentially in 16 bits. Thus, since no instruction from the processor every write-in of 1 bit is required, the write-in can quickly be completed.
JP6776880A 1980-05-23 1980-05-23 Monitor signal transmitting device Pending JPS56164646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6776880A JPS56164646A (en) 1980-05-23 1980-05-23 Monitor signal transmitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6776880A JPS56164646A (en) 1980-05-23 1980-05-23 Monitor signal transmitting device

Publications (1)

Publication Number Publication Date
JPS56164646A true JPS56164646A (en) 1981-12-17

Family

ID=13354443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6776880A Pending JPS56164646A (en) 1980-05-23 1980-05-23 Monitor signal transmitting device

Country Status (1)

Country Link
JP (1) JPS56164646A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111381838A (en) * 2018-12-28 2020-07-07 新唐科技股份有限公司 Data writing method, burning system, data updating method and storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111381838A (en) * 2018-12-28 2020-07-07 新唐科技股份有限公司 Data writing method, burning system, data updating method and storage device
CN111381838B (en) * 2018-12-28 2023-09-01 新唐科技股份有限公司 Data writing method, burning system, data updating method and storage device

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