JPS56162580A - Pll circuit - Google Patents

Pll circuit

Info

Publication number
JPS56162580A
JPS56162580A JP6627080A JP6627080A JPS56162580A JP S56162580 A JPS56162580 A JP S56162580A JP 6627080 A JP6627080 A JP 6627080A JP 6627080 A JP6627080 A JP 6627080A JP S56162580 A JPS56162580 A JP S56162580A
Authority
JP
Japan
Prior art keywords
circuit
output
frequency
phase comparator
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6627080A
Other languages
Japanese (ja)
Inventor
Ryusuke Moriya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP6627080A priority Critical patent/JPS56162580A/en
Publication of JPS56162580A publication Critical patent/JPS56162580A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number

Landscapes

  • Television Signal Processing For Recording (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To stabilize the operation of a PLL circuit by increasing its dynamic range by frequency-dividing and comparing the oscillation output of a variable frequency oscillator by extracting a certain period component in an input signal and then by using the component as the reference component as the reference comparison signal of a phase comparator. CONSTITUTION:An input digital signal Din is supplied to an automatic tuning circuit 63 via a differentiating circuit 61 and a full-wave rectifying circuit 62 and also applied to the phase comparator 71 of a charge pump type phase comparator 70. Further, a signal voltage VC which is generated from a reproduced signal and corresponds to a reproduction tape speed is applied to the circuit 63, whose output is frequency-divided by N at a frequency dividing circuit 65, the output of which is supplied to a delay circuit 66. Then, the phase of the output of a variable frequency oscillator 54 is compared with that of the input signal Din by the circuit 70, whose certain period output is applied to the circuit 66 and the output of the circuit is applied to a phase comparator 68 via a trapezoid-wave generating circuit 67, and the output of an oscillator 54 is phase-compared with the 1/N frequency- division output of a frequency divider 55, thereby stabilizing the operation of the titled PLL circuit.
JP6627080A 1980-05-19 1980-05-19 Pll circuit Pending JPS56162580A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6627080A JPS56162580A (en) 1980-05-19 1980-05-19 Pll circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6627080A JPS56162580A (en) 1980-05-19 1980-05-19 Pll circuit

Publications (1)

Publication Number Publication Date
JPS56162580A true JPS56162580A (en) 1981-12-14

Family

ID=13310978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6627080A Pending JPS56162580A (en) 1980-05-19 1980-05-19 Pll circuit

Country Status (1)

Country Link
JP (1) JPS56162580A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58107783A (en) * 1981-12-18 1983-06-27 アグフア−ゲ−ヴエルト・アクチエンゲゼルシヤフト Image recorder/reproducer
JPS59161924A (en) * 1983-03-07 1984-09-12 Nippon Telegr & Teleph Corp <Ntt> Phase synchronizing oscillator
JPS6052781U (en) * 1983-09-19 1985-04-13 横河電機株式会社 Digital video signal generator
JPH07142997A (en) * 1990-11-29 1995-06-02 Internatl Business Mach Corp <Ibm> Delay line calibration circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58107783A (en) * 1981-12-18 1983-06-27 アグフア−ゲ−ヴエルト・アクチエンゲゼルシヤフト Image recorder/reproducer
JPS59161924A (en) * 1983-03-07 1984-09-12 Nippon Telegr & Teleph Corp <Ntt> Phase synchronizing oscillator
JPS6052781U (en) * 1983-09-19 1985-04-13 横河電機株式会社 Digital video signal generator
JPH07142997A (en) * 1990-11-29 1995-06-02 Internatl Business Mach Corp <Ibm> Delay line calibration circuit

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