JPS5672544A - Frequency synthesizer system receiver - Google Patents
Frequency synthesizer system receiverInfo
- Publication number
- JPS5672544A JPS5672544A JP14917579A JP14917579A JPS5672544A JP S5672544 A JPS5672544 A JP S5672544A JP 14917579 A JP14917579 A JP 14917579A JP 14917579 A JP14917579 A JP 14917579A JP S5672544 A JPS5672544 A JP S5672544A
- Authority
- JP
- Japan
- Prior art keywords
- voltage control
- control oscillator
- omegan
- becomes
- frequency signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/10—Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path
Abstract
PURPOSE:To shorten the lock-up time of the PLL and make it possible to finely adjust the local oscillation frequency, by multiplying an oscillation output of the voltage control oscillator, and making it a reference frequency signal. CONSTITUTION:An oscillation output of the voltage control oscillator 13 is multiplied by M with the multiplier 16, and it is made a reference frequency signal M. fr (provided that fr is a conventional reference frequency signal). And when the oscillation output of the voltage control oscillator 13 is made fv, the dividing ratio can be made same as the conventional method, and the minimum variation frequency of the local oscillation frequency also becomes same as before. On the other hand, the natural angle frequency omegan' becomes the gain constant of omegan'=(M. KV.KP.KL/N)<12>=M<12>.omegan (provided that KV, KP and KL show the voltage control oscillator 13, the phase comparator 12 and the LPF15), it becomes M<12> times, and therefore the lock-up time can be made M<12> times.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14917579A JPS5672544A (en) | 1979-11-16 | 1979-11-16 | Frequency synthesizer system receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14917579A JPS5672544A (en) | 1979-11-16 | 1979-11-16 | Frequency synthesizer system receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5672544A true JPS5672544A (en) | 1981-06-16 |
Family
ID=15469430
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14917579A Pending JPS5672544A (en) | 1979-11-16 | 1979-11-16 | Frequency synthesizer system receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5672544A (en) |
-
1979
- 1979-11-16 JP JP14917579A patent/JPS5672544A/en active Pending
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