JPS57169868A - Video signal storage device - Google Patents

Video signal storage device

Info

Publication number
JPS57169868A
JPS57169868A JP5596381A JP5596381A JPS57169868A JP S57169868 A JPS57169868 A JP S57169868A JP 5596381 A JP5596381 A JP 5596381A JP 5596381 A JP5596381 A JP 5596381A JP S57169868 A JPS57169868 A JP S57169868A
Authority
JP
Japan
Prior art keywords
signal
frequency
clock
pll
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5596381A
Other languages
Japanese (ja)
Inventor
Junpei Kanazawa
Shinzo Shimomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Co Ltd
Original Assignee
Shinko Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Co Ltd filed Critical Shinko Electric Co Ltd
Priority to JP5596381A priority Critical patent/JPS57169868A/en
Publication of JPS57169868A publication Critical patent/JPS57169868A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/76Television signal recording
    • H04N5/907Television signal recording using static stores, e.g. storage tubes or semiconductor memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Image Input (AREA)
  • Closed-Circuit Television Systems (AREA)

Abstract

PURPOSE:To store a video signal of good quality by generating a clock signal which has a frequency and phase equal to the clock in an ITV on the basis of a received composite signal from the ITV. CONSTITUTION:A composite signal is received and separated into separate signals, and then the horizontal synchronizing signal HT has the input frequency (fin) of a PLL. Since the frequency and phase are disordered when the horizontal synchronizing signal HT disappears in, before, or after the vertical synchronizing signal VT, the PLL is inhibited before and after the signal VT. The PLL consists of a phase comparator 1 for comparing the input frequency (fin) with a feedback frequency (fp), a low-pass filter 2, a voltage-controlled oscillator 3 for converting a voltage signal from the filter 2 into a frequency signal proportional to its magnitude, and a frequency divider 4 for dividing the frequency fo of a clock from the oscillator 3.
JP5596381A 1981-04-13 1981-04-13 Video signal storage device Pending JPS57169868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5596381A JPS57169868A (en) 1981-04-13 1981-04-13 Video signal storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5596381A JPS57169868A (en) 1981-04-13 1981-04-13 Video signal storage device

Publications (1)

Publication Number Publication Date
JPS57169868A true JPS57169868A (en) 1982-10-19

Family

ID=13013732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5596381A Pending JPS57169868A (en) 1981-04-13 1981-04-13 Video signal storage device

Country Status (1)

Country Link
JP (1) JPS57169868A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6277682A (en) * 1985-09-30 1987-04-09 Hitachi Ltd Signal processor
JP2009024713A (en) * 2007-07-17 2009-02-05 Mazda Motor Corp Transmission

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6277682A (en) * 1985-09-30 1987-04-09 Hitachi Ltd Signal processor
JP2009024713A (en) * 2007-07-17 2009-02-05 Mazda Motor Corp Transmission

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