JPS56158460A - Resin sealed type semiconductor device - Google Patents

Resin sealed type semiconductor device

Info

Publication number
JPS56158460A
JPS56158460A JP6428480A JP6428480A JPS56158460A JP S56158460 A JPS56158460 A JP S56158460A JP 6428480 A JP6428480 A JP 6428480A JP 6428480 A JP6428480 A JP 6428480A JP S56158460 A JPS56158460 A JP S56158460A
Authority
JP
Japan
Prior art keywords
substrate
buried section
plastic
welded
projections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6428480A
Other languages
Japanese (ja)
Inventor
Tsutomu Kamata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6428480A priority Critical patent/JPS56158460A/en
Publication of JPS56158460A publication Critical patent/JPS56158460A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To obtain the resin sealed material having an excellent reliability by a method wherein a plastic buried section, with a plurality of projections around it, is provided on the whole circumference of the end face of a radiating metal substrate and on this buried section the end of a plastic tube is welded by performing a fusion welding. CONSTITUTION:On the upper half of a surface on the end face of the radiating metal substrate 14, the plastic buried section 15 is formed on the whole surface and at the tip of the buried section, a plurality of projections 16 are formed on the whole circumference. By heating the tip of the plastic tube 17 up to about 300 deg.C to obtain a fused or semifused condition and by applying pressure on the circumference of the substrate, the plastic buried section 15 having the projections 16 is enveloped and welded to the substrate 14 by performing a fusion welding in such manner that the end of the tube 17 reaches the end surface of the lower half of the substrate 14. According to this constitution, as the fusion welded surface of the substrate 14 and the plastic buried section 15 is wide, its adhesive strength is intensive, it is not peeled off at the temperature of 190 deg.C or thereabouts and an excellent reliability can be obtained.
JP6428480A 1980-05-12 1980-05-12 Resin sealed type semiconductor device Pending JPS56158460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6428480A JPS56158460A (en) 1980-05-12 1980-05-12 Resin sealed type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6428480A JPS56158460A (en) 1980-05-12 1980-05-12 Resin sealed type semiconductor device

Publications (1)

Publication Number Publication Date
JPS56158460A true JPS56158460A (en) 1981-12-07

Family

ID=13253773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6428480A Pending JPS56158460A (en) 1980-05-12 1980-05-12 Resin sealed type semiconductor device

Country Status (1)

Country Link
JP (1) JPS56158460A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5968955A (en) * 1982-10-13 1984-04-19 Nippon Denso Co Ltd Method for mounting thick film circuit substrate
JPS62140744U (en) * 1986-02-28 1987-09-05
JPH08282405A (en) * 1995-04-17 1996-10-29 Takigen Mfg Co Ltd Wiring device for door
US6214650B1 (en) 2000-02-01 2001-04-10 Lockheed Martin Corporation Method and apparatus for sealing a ball grid array package and circuit card interconnection
EP0921565A3 (en) * 1997-12-08 2005-07-27 Kabushiki Kaisha Toshiba Package for semiconductor power device and method for assembling the same
JPWO2018128005A1 (en) * 2017-01-06 2019-11-07 パナソニックIpマネジメント株式会社 Capacitor, capacitor unit, capacitor manufacturing method, and capacitor unit manufacturing method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5968955A (en) * 1982-10-13 1984-04-19 Nippon Denso Co Ltd Method for mounting thick film circuit substrate
JPH0237100B2 (en) * 1982-10-13 1990-08-22 Nippon Denso Co
JPS62140744U (en) * 1986-02-28 1987-09-05
JPH0412677Y2 (en) * 1986-02-28 1992-03-26
JPH08282405A (en) * 1995-04-17 1996-10-29 Takigen Mfg Co Ltd Wiring device for door
EP0921565A3 (en) * 1997-12-08 2005-07-27 Kabushiki Kaisha Toshiba Package for semiconductor power device and method for assembling the same
US6214650B1 (en) 2000-02-01 2001-04-10 Lockheed Martin Corporation Method and apparatus for sealing a ball grid array package and circuit card interconnection
US6459164B2 (en) 2000-02-01 2002-10-01 Lockheed Martin Corporation Apparatus for sealing a ball grid array package and circuit card interconnection
JPWO2018128005A1 (en) * 2017-01-06 2019-11-07 パナソニックIpマネジメント株式会社 Capacitor, capacitor unit, capacitor manufacturing method, and capacitor unit manufacturing method

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