JPS6418245A - Ceramic substrate having metal pin and its manufacture - Google Patents

Ceramic substrate having metal pin and its manufacture

Info

Publication number
JPS6418245A
JPS6418245A JP62174180A JP17418087A JPS6418245A JP S6418245 A JPS6418245 A JP S6418245A JP 62174180 A JP62174180 A JP 62174180A JP 17418087 A JP17418087 A JP 17418087A JP S6418245 A JPS6418245 A JP S6418245A
Authority
JP
Japan
Prior art keywords
brazing material
metal pin
alloy layer
bonding
ceramic substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62174180A
Other languages
Japanese (ja)
Other versions
JPH0783083B2 (en
Inventor
Takashi Fukumaki
Katsuhiko Shioda
Kyo Matsuzaka
Tomohiko Shida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62174180A priority Critical patent/JPH0783083B2/en
Publication of JPS6418245A publication Critical patent/JPS6418245A/en
Publication of JPH0783083B2 publication Critical patent/JPH0783083B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Products (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance the bonding strength and the thermal resistance by a method wherein an alloy layer is formed on a bonding face between a ceramic substrate and a metal pin. CONSTITUTION:A brazing material 6 is pasted to a metal film 2; then, the pasted brazing material 6 is brought into contact with a lower end of a metal pin 3 which has been erected in its axial direction; an electric current is applied to a contacted joint part; this part is heated; the brazing material 6 is melted; the metal pin 3 is pressurized; the joint part is bonded. An alloy layer 9 formed together with the brazing material 6 is formed on the metal film 2; the alloy layer 9 formed together with the brazing material 6 is formed on the metal pin 3; these individual alloy layers 9 are heated and pressurized; the brazing material 6 whose melting point is lower is squeezed; a bonding operation is executed. While the bonding operation is executed at a temperature which is lower than that of a conventional operation, the alloy layer 9 whose remelting point is higher than a melting point of the brazing material 6 remains at a bonding face between the metal pin 3 and the metal film 2. By this setup, the bonding strength and the thermal resistance are enhanced.
JP62174180A 1987-07-13 1987-07-13 Ceramic board having metal pins and method of manufacturing the same Expired - Lifetime JPH0783083B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62174180A JPH0783083B2 (en) 1987-07-13 1987-07-13 Ceramic board having metal pins and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62174180A JPH0783083B2 (en) 1987-07-13 1987-07-13 Ceramic board having metal pins and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPS6418245A true JPS6418245A (en) 1989-01-23
JPH0783083B2 JPH0783083B2 (en) 1995-09-06

Family

ID=15974112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62174180A Expired - Lifetime JPH0783083B2 (en) 1987-07-13 1987-07-13 Ceramic board having metal pins and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JPH0783083B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03141662A (en) * 1989-10-26 1991-06-17 Matsushita Electric Works Ltd Manufacture of ceramic wiring circuit board
JP2002362982A (en) * 2001-06-08 2002-12-18 Tokai Konetsu Kogyo Co Ltd Joint structure of conductive ceramic to electrode terminal and manufacturing method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007037184A1 (en) * 2005-09-28 2007-04-05 Neomax Materials Co., Ltd. Process for producing electrode wire for solar battery

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083356A (en) * 1983-10-14 1985-05-11 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083356A (en) * 1983-10-14 1985-05-11 Hitachi Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03141662A (en) * 1989-10-26 1991-06-17 Matsushita Electric Works Ltd Manufacture of ceramic wiring circuit board
JP2002362982A (en) * 2001-06-08 2002-12-18 Tokai Konetsu Kogyo Co Ltd Joint structure of conductive ceramic to electrode terminal and manufacturing method thereof

Also Published As

Publication number Publication date
JPH0783083B2 (en) 1995-09-06

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