JPH0783083B2 - Ceramic board having metal pins and method of manufacturing the same - Google Patents

Ceramic board having metal pins and method of manufacturing the same

Info

Publication number
JPH0783083B2
JPH0783083B2 JP62174180A JP17418087A JPH0783083B2 JP H0783083 B2 JPH0783083 B2 JP H0783083B2 JP 62174180 A JP62174180 A JP 62174180A JP 17418087 A JP17418087 A JP 17418087A JP H0783083 B2 JPH0783083 B2 JP H0783083B2
Authority
JP
Japan
Prior art keywords
metal
ceramic substrate
metal pin
pin
brazing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62174180A
Other languages
Japanese (ja)
Other versions
JPS6418245A (en
Inventor
孝 服巻
勝彦 塩田
矯 松坂
朝彦 志田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62174180A priority Critical patent/JPH0783083B2/en
Publication of JPS6418245A publication Critical patent/JPS6418245A/en
Publication of JPH0783083B2 publication Critical patent/JPH0783083B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Products (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、セラミツク基板あるいはプリント基板等の配
線基板に信号入出力用端子として用いるピンの接続に好
適な高強度でかつ耐熱性に優れる金属ピンを有するセラ
ミツク基板とその製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a metal having high strength and excellent heat resistance suitable for connecting pins used as signal input / output terminals to wiring boards such as ceramic boards or printed boards. The present invention relates to a ceramic board having pins and a method for manufacturing the same.

〔従来の技術〕[Conventional technology]

従来、セラミツク基板あるいはプリント基板等の配線基
板に信号の入出力端子として用いられるピンをろう材に
より接合している。この場合、セラミツク基板のピン接
合面は予め金属化してあり、金属細線のピンと銀ろう付
けする特開昭59−26985号公報、特開昭59−35075号公報
がすでに知られている。しかしこれらの方法は接合温度
が約800℃と高いため、熱膨張率の異なるセラミツクス
と金属との間に大きな熱応力が生じて延性のないセラミ
ツクスが破壊してしまう問題があつた。このようなセラ
ミツクスの熱応力破壊を防止する方法として、例えばAl
2O3等の酸化物系セラミツクの場合は、金属との間に熱
膨張率が両者のほぼ中間の中間材を介して接合する方法
がある。この中間材として熱膨張率が5〜8×10-6/℃
のNi−Fe合金等が採用されている。
Conventionally, a pin used as a signal input / output terminal is joined to a wiring board such as a ceramic board or a printed board with a brazing material. In this case, Japanese Patent Laid-Open Nos. 59-26985 and 59-35075 are already known in which the pin-bonding surface of the ceramic substrate is metallized in advance and silver brazing is performed on the pins of the thin metal wires. However, in these methods, since the joining temperature is as high as about 800 ° C., there is a problem that a large thermal stress is generated between the ceramics having different thermal expansion coefficients and the metal, and the non-ductile ceramics are destroyed. As a method of preventing thermal stress destruction of such ceramics, for example, Al
In the case of oxide-based ceramics such as 2 O 3 or the like, there is a method of joining with a metal via an intermediate material having a coefficient of thermal expansion approximately in between. This intermediate material has a coefficient of thermal expansion of 5-8 × 10 -6 / ° C.
Ni-Fe alloys are used.

しかし前記中間材を使用した場合でもその熱膨率は室温
から約400℃の温度範囲においては、比較的小さいが、4
00℃以上では急激に増加するため、ろう材JISBAg8(Ag
−28%Cu)でろう付けした場合、接合過程で生じる熱応
力の発生がさけられず、セラミツクスの熱応力破壊を完
全に防止することは困難であつた。また接合過程でセラ
ミツクスに熱応力破壊が生じないまでも残留応力が残
り、これが原因で使用中にセラミツクスが破壊する原因
となつていた。一方、SiC,Si3N4,サイアロン等の非酸化
物系セラミツクスの場合は熱膨張率が4×10-6/℃以下
でAl2O3等の酸化物系に比較して小さい為、両者を接合
する場合も前期中間材では熱応力破壊を防止することは
更に出来なくなる。また接合が多数のピンを同時にしか
も800℃と高い温度で行われる為に細線の金属ピンが焼
鈍され、硬度が低下し、ピンの接合強度も高くなかつた
ので、使用中にピンの折曲りや接合部の破損等が生じる
欠点があつた。
However, even when the above intermediate material is used, its coefficient of thermal expansion is relatively small in the temperature range from room temperature to about 400 ° C.
Since it rapidly increases above 00 ° C, brazing filler metal JISBAg8 (Ag
In the case of brazing with -28% Cu), the generation of thermal stress in the joining process was unavoidable, and it was difficult to completely prevent the thermal stress destruction of the ceramics. Further, residual stress remains in the ceramics even if thermal stress fracture does not occur during the joining process, which causes the ceramics to break during use. On the other hand, in the case of non-oxide type ceramics such as SiC, Si 3 N 4 and sialon, the coefficient of thermal expansion is 4 × 10 −6 / ° C or less, which is smaller than that of oxide type such as Al 2 O 3 , so both Even in the case of joining, it becomes impossible to prevent thermal stress fracture with the intermediate material in the previous term. Also, since many pins are joined at the same time and at a high temperature of 800 ° C, the thin metal pin is annealed, the hardness is reduced, and the joint strength of the pin is not high. There was a defect that the joint part was damaged.

これらの問題点及び欠点を防止する接合方法として、銀
ろうより低温で接合可能なはんだ材を用いる方法があ
る。しかしはんだ材等を用いて低温で接合した場合に
は、接合部の強度が低下するばかりでなく耐熱性が劣
り、使用範囲が制限されるという欠点がある。
As a joining method for preventing these problems and drawbacks, there is a method of using a solder material that can be joined at a lower temperature than silver solder. However, when a solder material or the like is used for joining at a low temperature, not only the strength of the joining portion is lowered but also the heat resistance is deteriorated, which limits the use range.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

本発明の目的は、前記欠点をなくし接合強度が低下せ
ず、金属ピンの焼鈍効果が少なく更に基板のそりが小さ
くかつ耐熱性に優れる金属ピンを有すセラミツク基板と
その製造方法を提供するにある。
An object of the present invention is to provide a ceramic substrate having a metal pin that eliminates the above-mentioned drawbacks, does not reduce the bonding strength, has a small annealing effect on the metal pin, has a small warpage of the substrate, and has excellent heat resistance, and a method for manufacturing the same. is there.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的はセラミックスと、該セラミックス上に被覆さ
れた金属被膜と、該金属被膜上に立設する金属ピンを接
合したセラミック基板において、前記金属ピンと前記金
属被膜とを、前記金属ピン表面の成分と前記金属被膜の
成分と融点が400℃以下のろう材の成分とからなり再溶
融温度が600℃以上の合金層により直接接合したことに
より達成される。
The above-mentioned object is a ceramic substrate in which ceramics, a metal coating film coated on the ceramics, and metal pins standing on the metal coating are joined, and the metal pin and the metal coating are the components of the surface of the metal pin. This can be achieved by directly joining by an alloy layer composed of the components of the metal coating and the components of the brazing filler metal having a melting point of 400 ° C or lower and having a remelting temperature of 600 ° C or higher.

上記目的は、セラミック基板に形成された金属被膜上に
金属ピンをその軸方向に立てて接合する金属ピンを有す
るセラミック基板の製造方法において、金属被膜に融点
が400℃以下のろう材を付着させ、次いで付着したろう
材と金属ピンを軸方向に立てた下端とを接触させて金属
ピンに通電して加熱し、ろう材を溶融させて金属ピン表
面の成分と金属被膜の成分とろう材の成分とからなり再
溶融温度が600℃以上の合金層を形成し、金属ピンを金
属ピンの軸方向に加圧してろう材を排除し、金属被膜と
金属ピンを合金層により直接接合することにより達成さ
れる。
The above-mentioned object is a method for manufacturing a ceramic substrate having a metal pin in which a metal pin is erected in the axial direction on a metal film formed on the ceramic substrate and joined, in which a brazing material having a melting point of 400 ° C. or less is attached to the metal film. Then, the attached brazing filler metal and the lower end of the metal pin standing in the axial direction are brought into contact with each other, and the metal pin is heated by energization to melt the brazing filler metal, thereby melting the components of the metal pin surface and the metal coating and the brazing filler metal. By forming an alloy layer consisting of the components and having a remelting temperature of 600 ℃ or higher, press the metal pin in the axial direction of the metal pin to eliminate the brazing material, and directly bond the metal coating and the metal pin by the alloy layer. To be achieved.

〔作用〕[Action]

金属被膜にろう材を付着させろう材との合金層を形成さ
せ、同様に金属ピンにろう材を付着させろう材との合金
層を形成させ、その各々の金合金を加熱,加圧して溶融
点の低いろう材を排出して接合させる。
A brazing material is attached to the metal film to form an alloy layer with the brazing material, and a brazing material is also attached to the metal pins to form an alloy layer with the brazing material, and each of the gold alloys is heated and pressed to melt. The brazing filler metal with a low point is discharged and joined.

接合はろう材の溶融する従来より低い温度で行なわれる
一方再溶融点がろう材の溶融点より高い合金層が金属ピ
ンと金属被膜の接合面に残る。
The joining is performed at a lower temperature than the conventional melting temperature of the brazing material, while an alloy layer having a remelting point higher than the melting point of the brazing material remains on the joining surface between the metal pin and the metal coating.

〔実施例〕〔Example〕

以下、本発明の実施例を説明する。 Examples of the present invention will be described below.

本発明の特徴として溶融点の低いろう材を用いることで
あり、ろう材として溶融点の低いものが必要な場合、芝
晶成分またはその近傍成分を選ぶことは一般的に用いる
手法である。400℃以下で接合材間に合金層を形成する
に好ましいろう材として第1表にかかげる組合せが考え
られる。
A feature of the present invention is that a brazing material having a low melting point is used, and when a brazing material having a low melting point is required, selecting a turf crystal component or a component in the vicinity thereof is a commonly used method. As a preferable brazing material for forming an alloy layer between the joining materials at 400 ° C. or lower, the combinations shown in Table 1 can be considered.

次にセラミツク基板へのピン接合方法について説明す
る。
Next, a method for joining pins to the ceramic substrate will be described.

第1実施例 多層Al2O3セラミツク基板に金属細線のピンを本発明の
接合方法で接合した部分の外観第1a図と、片面に予めろ
う付して本接合する前の断面図第b図及び本接合をした
断面図第1c図を示す。すなわち50mm角の多層セラミツク
基板1のメタライズパツド2の箇所に金属細線0.7φの
金属ピン3を接合する。詳しくはセラミツク基板1のメ
タライズパツド2はタングステン4を焼成してメタライ
ズされ、その上にNiメツキ5が施されている。そして本
発明の接合がより容易になるようにこれらメタライズ面
に予めはんだ付6を施す。この方法は作業性に優れる。
溶融したはんだ浴の中にメタライズされたセラミツク基
板1を浸漬することによつて達成される。このはんだ付
によつてNiメツキ5とはんだの界面に合金層7が形成さ
れる。用いたはんだはSn50−Pb50であり、はんだ付は25
0℃で数秒かけた為Ni−Snの合金属の厚みが数μm形成
され、合金層7の表面は未反応のはんだが20μm覆つて
いる状態である。次に金属ピン3を載置し本接合に入
る。加熱は抵抗溶接の電極8を用いて行い、350〜450℃
の範囲で加熱する。この段階では加圧力は意識的に付与
せず、通電電流により加熱し、第1c図に示すようにピン
側にも合金層9を形成させる。加熱の方法については電
極8による金属ピン3の局部加熱以外にもセラミツク基
板1と金属ピン全体を加熱することを考えられる。金属
ピン3側に合金層7が0.5μm形成された時点で次に電
極8によつて加圧する。加圧力は2〜5kgf/mm2で行つ
た。この接合過程を経ることにより両接合材に形成され
た合金層9が近接し接合される。ここに形成された合金
層の厚みは2〜5μmであつた。この合金層9は接合材
母材とはんだ成分のSnと反応した相である為ろうの液相
点に比較し溶融点が高くなつている。即ち、溶融点の低
い未反応のSn−Pbは合金層中には見られない。一方ろう
付温度で溶融している未反応のはんだ成分は2〜5kgf/m
m2の加圧力により接合面外へ排出ろう材10として排出さ
れる。そしてその量にもよるが排出はんだは取除く。そ
の除去は、はんだが溶融中に真空吸引で行う方法または
吹飛し方法で行う。また予め付着させるろうが5μm以
下と極めて薄い場合はそのままでも製品とすることも可
能である。
First Embodiment FIG. 1a is an external view of a portion where a thin metal wire pin is joined to a multilayer Al 2 O 3 ceramic substrate by the joining method of the present invention, and a sectional view before the main joining by brazing to one side in advance. FIG. 1c is a cross-sectional view showing the main joining. That is, a metal pin 3 having a fine metal wire of 0.7φ is joined to the metallized pad 2 of the 50 mm square multilayer ceramic substrate 1. More specifically, the metallized pad 2 of the ceramic substrate 1 is metallized by firing tungsten 4, and Ni plating 5 is applied thereon. Then, soldering 6 is applied in advance to these metallized surfaces so that the joining of the present invention becomes easier. This method is excellent in workability.
This is accomplished by immersing the metallized ceramic substrate 1 in a molten solder bath. By this soldering, the alloy layer 7 is formed at the interface between the Ni plating 5 and the solder. The solder used was Sn50-Pb50, and soldering was 25
Since it took several seconds at 0 ° C., the thickness of the Ni—Sn composite metal was formed to several μm, and the surface of the alloy layer 7 was covered with unreacted solder of 20 μm. Next, the metal pin 3 is placed and the main joining is started. Heating is performed using resistance welding electrode 8 at 350-450 ° C
Heat in the range. At this stage, the applied pressure is not intentionally applied, but the applied current is used to heat the alloy layer 9 on the pin side as shown in FIG. 1c. Regarding the heating method, it is conceivable to heat the ceramic substrate 1 and the entire metal pin in addition to the local heating of the metal pin 3 by the electrode 8. When the alloy layer 7 is formed on the metal pin 3 side by 0.5 μm, pressure is applied by the electrode 8 next. The applied pressure was 2 to 5 kgf / mm 2 . Through this joining process, the alloy layers 9 formed on both joining materials come close to each other and are joined. The thickness of the alloy layer formed here was 2 to 5 μm. This alloy layer 9 has a higher melting point than the liquid phase point of the brazing material because it is a phase that has reacted with the bonding material base material and Sn of the solder component. That is, unreacted Sn-Pb having a low melting point is not found in the alloy layer. On the other hand, the unreacted solder component that melts at the brazing temperature is 2 to 5 kgf / m
The brazing filler metal 10 is discharged to the outside of the joint surface by the pressing force of m 2 . Then, depending on the amount, remove the discharged solder. The removal is performed by a vacuum suction method or a blowing method while the solder is melting. Further, if the wax to be adhered in advance is extremely thin as 5 μm or less, it can be used as it is as a product.

第2実施例 第2a図に接合する前の組立てた様子を、第2b図に接合後
の様子を示す。ここではろう付がうまく行くようにAl2O
3基板のNiメツキ5の上に更にAuメツキ11を、一方のFe
−Ni合金ピンの上にAuメツキ12が施されている。ろう材
には第1表にあげたAu−6Si箔13をはさんだ。次に本発
明の本接合に入る。本接合は第1実施例の過程とほぼ同
様な条件で行うと両母材の接合界面にそれぞれ合金層が
形成され合金層14で接合される。本法によつて未反応の
Au−Si成分が接合面外へ排出ろう材15として排出され
る。そして排出したろう材は取除き、その方法は前記し
た通りである。
Second Embodiment FIG. 2a shows the assembled state before joining, and FIG. 2b shows the assembled state. Al 2 O here for brazing to work
3 Au plating 11 on top of Ni plating 5 on one substrate and Fe on one side
-Au plating 12 is applied on the Ni alloy pin. The brazing filler metal is the Au-6Si foil 13 listed in Table 1. Next, the main joining of the present invention is started. If the main joining is performed under substantially the same conditions as in the process of the first embodiment, an alloy layer is formed at the joining interface between both base materials, and the alloy layers 14 are joined. Unreacted by this method
The Au-Si component is discharged as a brazing filler metal 15 out of the joint surface. Then, the discharged brazing material is removed, and the method is as described above.

第3実施例 多層セラミツク基板は第1実施例と同じで、相手のピン
材にコバールを用い、その上に同様にAuメツキを施して
ある。またろう材にAu−20Sn箔を用い、第2実施例と同
様な接合過程を経て本接合を終える。その時未反応のAu
−Sn成分も排出される。
Third Embodiment The multilayer ceramic substrate is the same as that of the first embodiment, and Kovar is used as the mating pin material, and Au plating is similarly applied thereto. The Au-20Sn foil is used as the brazing material, and the main joining is completed through the same joining process as in the second embodiment. Unreacted Au at that time
-Sn component is also discharged.

第4実施例 半導体のPGA(ピングリツドアレイ)を例にして本発明
の適用を説明する。第3図にPGAパツケージの断面構造
を示す。PGAは図に示すように裏側に信号入出力用の金
属ピン3が格子状に多数接続された多層配線Al2O3セラ
ミツク基板1とSiチツプ30が塔載されるSiC等の放熱板4
0とが接合され更にコバール等の封止材50により封止さ
れた構造となつている。第4図は本発明の方法で接続し
たPGAのA部拡大図を示す。即ち、多層Al2O3基板1のメ
タライズパツド2の箇所にコバールの金属ピン3を接合
する。詳しくはセラミツク基板1のメタライズパツド2
は、タングステン4を焼成してメタライズされ、その上
にNiメツキ5が、更にその上にAuメツキ11が施されてい
る。一方コバールの金属ピン3の表面にもAuメツキ12が
施され、これらの両者をSn50−Pb50はんだを用い(予め
はんだ付を250℃、10秒間行つている)、通電加圧,加
圧装置により450℃以下に加熱し、同時に4kgf/mm2の加
圧を付与した。この操作により3μm厚の合金層14で接
合された。つまり最初のSn50−Pb50はんだ中のSnとメツ
キのAuとが反応してAu−Sn合金層を形成する。そして溶
融時の加圧によつて未反応のSnとPbが接合面外へ排出ろ
う材15として排出され、接合時の加熱温度より高くなつ
ているAu−Sn成分層が残つて合金層接合となる。この結
果AuとSnの反応によりAuメツキが溶食されメツキの厚み
が薄くなる。
Fourth Embodiment Application of the present invention will be described by taking a semiconductor PGA (Pinging Array) as an example. Figure 3 shows the cross-sectional structure of the PGA package. PGA is the heat sink 4 of SiC such that the multilayer wiring Al 2 O 3 ceramic substrate 1 and the Si chip 30 is metal pin 3 for signal input and output on the back side are connected a number in a lattice form as shown in the figure is the tower
0 is joined and further sealed by a sealing material 50 such as Kovar. FIG. 4 shows an enlarged view of part A of the PGA connected by the method of the present invention. That is, the metal pin 3 of Kovar is bonded to the metallized pad 2 of the multilayer Al 2 O 3 substrate 1. For details, see the metallized pad 2 on the ceramic substrate 1.
Is metallized by firing tungsten 4, Ni plating 5 is formed on it, and Au plating 11 is formed on it. On the other hand, Au plating 12 is also applied to the surface of Kovar's metal pin 3, and Sn50-Pb50 solder is used for both of these (preliminarily soldering is performed at 250 ° C. for 10 seconds) by means of a current pressure and pressure device. It was heated to 450 ° C. or lower and a pressure of 4 kgf / mm 2 was applied at the same time. By this operation, the alloy layer 14 having a thickness of 3 μm was bonded. That is, Sn in the first Sn50-Pb50 solder reacts with Au in the plating to form an Au-Sn alloy layer. And unreacted Sn and Pb are discharged out of the joint surface as the brazing filler metal 15 by pressurization at the time of melting, and the Au-Sn component layer which is higher than the heating temperature at the time of joining remains as an alloy layer joint. Become. As a result, the Au plating is eroded by the reaction between Au and Sn, and the thickness of the plating becomes thin.

第1比較例 第1実施例と同じメタライズしたAl2O3基板と金属細線
のピンをAg−Cu28の高温銀ろう箔を用いて810℃で炉中
ろう付した。これは一般的なろう付方法なので当然加圧
はしていない。
First Comparative Example The same metallized Al 2 O 3 substrate and fine metal wire pins as in the first example were brazed in a furnace at 810 ° C. using a Ag—Cu 28 high temperature silver brazing foil. Since this is a general brazing method, no pressure is applied.

第2比較例 第1実施例と同じメタライズしたAl2O3基板と金属細線
のピンをSn50−Pb50の低温ろう箔をはさみ250℃でフラ
ツクスを用いて炉中ろう付した。これも一般的なろう付
方法なので当然加圧はしていない。
Second Comparative Example The same metallized Al 2 O 3 substrate and thin metal wire pins as in the first example were sandwiched between Sn50-Pb50 low temperature brazing foils and brazed in a furnace at 250 ° C. using a flux. Since this is also a general brazing method, no pressure is applied.

以上の実施例の3例と比較例の2例の方法で接合した継
手の特性試験を行つた。第5図に引張試験結果を示す。
試験片は各々の条件下で3ケずつ製作し、それらを破断
荷重で表わす。本発明の実施例では3例とも大差なく、
5〜6kgの範囲と安定した高い強さを示した。一方比較
例では高温の銀ろうを用いて接合した継手の方がSn50−
Pb50の低温ろうで接合した継手よりも継手強度は高い。
しかし本発明に比較すると銀ろうの継手でもやや弱い。
この原因はセラミツクとメタライズの界面に極めて小さ
いミクロ割れが認められ、それがやや弱くなつた原因と
考える。ミクロ割れは800℃と高い温度に加熱されるの
で接合部に熱応力が生じたものであろう。
A characteristic test was performed on the joints joined by the methods of the above-described three examples and two comparative examples. FIG. 5 shows the tensile test results.
Three test pieces were produced under each condition, and they are expressed by breaking load. In the embodiment of the present invention, there is no great difference between the three cases,
It showed stable high strength in the range of 5-6 kg. On the other hand, in the comparative example, the Sn50-
The joint strength is higher than that of joints joined with low temperature brazing of Pb50.
However, compared with the present invention, the joint of silver solder is also slightly weak.
It is considered that the cause of this is that extremely small micro-cracks were observed at the interface between the ceramic and the metallization, and that they were slightly weakened. Since the micro-cracks are heated to a high temperature of 800 ° C, thermal stress may have occurred at the joint.

本発明の接合方法によれば高い安定した接合強度が得ら
れることが明らかとなつた。この原因を明らかにするた
めに本発明の方法で接合した継手の断面をEPMA(電子プ
ローブマイクロアナライザ)で分析したところ、第1実
施例ではFe−Ni−Sn合金属が3μm形成されており、ろ
う材の主成分のPbは検出されなかつた。第2実施例では
Au−Siが主でわずかにFe,Niも認められその厚みは4μ
mであつた。第3実施例ではAu−Snが主で、その他わず
かにFe,Ni及びCoが認められその厚みは5μmであつ
た。即ちこれらの合金層は従来のろう付法と比較すると
極めて薄く、なおかつ接合母材と反応した層なので融点
も高くなつており、従つて接合部の耐熱性及び引張強度
が一段と向上したものと考える。50mm角のAl2O3セラミ
ツク基板面のそりについて測定したものが第6図であ
る。この結果によると第1比較例の高温の銀ろうでろう
付したものが最もそりの値が大きく、20μmもある。第
2比較例のSn−Pbはんだは、ろう付温度が低いためそり
も小さく、5μmの値を示した。それに対し本発明の実
施例1〜3迄の基板面のそりは小さい値で安定してお
り、その値は5μm以下である。Sn−Pbよりわずかに低
い値を示しているのは本発明の接合方法が抵抗加熱,加
圧装置を用いていることから基板の加熱が小さかつたこ
とに起因しているものと考えられる。
It has been clarified that the bonding method of the present invention can provide high and stable bonding strength. In order to clarify the cause, a cross section of the joint joined by the method of the present invention was analyzed by EPMA (electron probe microanalyzer). As a result, Fe-Ni-Sn composite metal was formed to 3 μm in the first embodiment. The main component of brazing material, Pb, was not detected. In the second embodiment
Au-Si is the main, and Fe and Ni are slightly recognized, and its thickness is 4μ.
It was m. In the third example, Au-Sn was the main component, and Fe, Ni and Co were slightly observed, and the thickness was 5 μm. That is, these alloy layers are extremely thin as compared with the conventional brazing method, and since they are layers that have reacted with the joining base metal, their melting points are also high, and accordingly, it is considered that the heat resistance and tensile strength of the joining portion are further improved. . FIG. 6 shows a measurement of the warp of the Al 2 O 3 ceramic substrate surface of 50 mm square. According to this result, the value of the warp of the first comparative example brazed with the high temperature silver brazing material is the largest, and is as large as 20 μm. The Sn-Pb solder of the second comparative example had a small brazing temperature and thus had a small warpage, and showed a value of 5 μm. On the other hand, the warpage of the substrate surface in Examples 1 to 3 of the present invention is stable at a small value, and the value is 5 μm or less. The slightly lower value than Sn-Pb is considered to be due to the fact that the heating of the substrate was small because the bonding method of the present invention uses a resistance heating and pressurizing device.

以上の実施例の他に、リン青銅ピンあるいはメタライズ
されたムライト基板等の組合せでも本発明の方法は適用
できる。第1表にあげた以外のろう材も同様比較的低温
で接合ができ、かつ接合強度を向上させるものである。
その他のろう材、Au−Ge等の比較的溶融点の低いものも
本発明の方法が適用できる。通電加熱,加圧装置以外に
レーザ及び光ビーム等を熱源とし別に加圧装置を配置し
て行つても本発明の方法は完遂できる。
In addition to the above embodiments, the method of the present invention can be applied to a combination of phosphor bronze pins or a metallized mullite substrate. Similarly, brazing filler metals other than those listed in Table 1 can be joined at a relatively low temperature and improve the joint strength.
The method of the present invention can be applied to other brazing filler metals, such as Au-Ge, which have a relatively low melting point. The method of the present invention can be accomplished by using a laser, a light beam or the like as a heat source in addition to the electric heating and pressurizing device and separately disposing a pressurizing device.

〔効果〕〔effect〕

本発明の製造方法によれば、低い温度でセラミツク基板
上の金属被膜と金属ピンを接合できるので、セラミツク
基板の製造時の熱応力による破壊及び変形,残留応力に
よる使用中の破損,金属ピンの焼鈍効果による硬度低下
がもたらす使用中の変形を防止し、セラミツク基板と金
属ピンの接合面に合金層が形成されるので接合強度が従
来の製法より増大し信頼性の高い金属ピンを有するセラ
ミツク基板を提供できる効果がある。
According to the manufacturing method of the present invention, since the metal coating on the ceramic substrate and the metal pin can be bonded at a low temperature, destruction and deformation due to thermal stress at the time of manufacturing the ceramic substrate, damage during use due to residual stress, and metal pin Prevents deformation during use caused by hardness reduction due to the annealing effect, and since an alloy layer is formed on the bonding surface between the ceramic substrate and the metal pin, the bonding strength is higher than in the conventional manufacturing method and the ceramic substrate has a highly reliable metal pin. There is an effect that can be provided.

【図面の簡単な説明】[Brief description of drawings]

第1a図が本発明の実施例を示す外観図、第1b図がメタラ
イズされたセラミツクスの基板側に予めはんだ付をして
他方の金属ピンと対面させ抵抗加熱,加圧装置に設置し
た断面図、第1c図は抵抗加熱,加圧をして接合した直後
の断面図、第2a図はメタライズされたセラミツクスの基
板及び金属ピンにAuメツキを施し、低融点ろう材をはさ
み、抵抗加熱,加圧装置に設置した断面図、第2b図は抵
抗加熱,加圧をして接合した直後の断面図、第3図はピ
ングリツドアレイパツケージの構造断面図、第4図はピ
ングリツドアレイのピンとメタライズされたセラミツク
スを接合した直後の断面図、第5図は本発明の方法と従
来の方法で接合した継手の引張試験結果を示す図、第6
図は本発明の方法と従来の方法で接合した後のセラミツ
ク基板面のそりを測定した図である。 1……セラミツク基板、2……金属被膜、3……金属ピ
ン、6……ろう材、8……電極、9……合金層。
FIG. 1a is an external view showing an embodiment of the present invention, FIG. 1b is a cross-sectional view of a metallized ceramic substrate that is pre-soldered to face the other metal pin and is placed in a resistance heating / pressurizing device. Fig. 1c is a cross-sectional view immediately after resistance heating and pressurizing and joining, and Fig. 2a is Au plating on the metallized ceramic substrate and metal pins, sandwiching low melting point brazing filler metal, and resistance heating and pressing. Fig. 2b is a sectional view immediately after joining by resistance heating and pressurization, Fig. 3 is a sectional view of the structure of the pin grid array package, and Fig. 4 is a pin of the pin grid array. FIG. 6 is a sectional view immediately after joining the metallized ceramics, FIG. 5 is a diagram showing tensile test results of joints joined by the method of the present invention and the conventional method, and FIG.
The figure is a diagram in which the warpage of the ceramic substrate surface after the bonding by the method of the present invention and the conventional method is measured. 1 ... Ceramic substrate, 2 ... Metal film, 3 ... Metal pin, 6 ... Brazing material, 8 ... Electrode, 9 ... Alloy layer.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 志田 朝彦 茨城県日立市久慈町4026番地 株式会社日 立製作所日立研究所内 (56)参考文献 特開 昭60−83356(JP,A) 特開 昭62−63454(JP,A) 特開 昭63−104460(JP,A) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Asahiko Shida 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-60-83356 (JP, A) JP-A-62 -63454 (JP, A) JP-A-63-104460 (JP, A)

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】セラミックスと、該セラミックス上に被覆
された金属被膜と、該金属被膜上に立設する金属ピンを
接合したセラミック基板において、 前記金属ピンと前記金属被膜とを、前記金属ピン表面の
成分と前記金属被膜の成分と融点が400℃以下のろう材
の成分とからなり再溶融温度が600℃以上の合金層によ
り直接接合したことを特徴とする金属ピンを有するセラ
ミック基板。
1. A ceramic substrate in which ceramics, a metal coating film coated on the ceramics, and a metal pin standing on the metal coating are joined, wherein the metal pin and the metal coating are formed on the surface of the metal pin. A ceramic substrate having metal pins, characterized in that it is directly bonded by an alloy layer having a remelting temperature of 600 ° C. or higher, which is composed of a component, the metal coating component, and a brazing filler metal component having a melting point of 400 ° C. or lower.
【請求項2】前記ろう材が錫、錫と鉛、金、珪素、亜鉛
のうち少なくとも1種とからなる合金、金と珪素とから
なる合金、ビスマス、鉛、銀、亜鉛からなる合金の何れ
かであることを特徴とする特許請求の範囲第1項記載の
金属ピンを有するセラミック基板。
2. The brazing material is any one of tin, an alloy containing tin and lead, at least one of gold, silicon and zinc, an alloy containing gold and silicon, and an alloy containing bismuth, lead, silver and zinc. A ceramic substrate having metal pins according to claim 1, characterized in that
【請求項3】前記合金層の厚さが0.5〜5μmであるこ
とを特徴とする特許請求の範囲第1項記載の金属ピンを
有するセラミック基板。
3. The ceramic substrate having metal pins according to claim 1, wherein the alloy layer has a thickness of 0.5 to 5 μm.
【請求項4】セラミック基板に形成された金属被膜上に
金属ピンをその軸方向に立てて接合する金属ピンを有す
るセラミック基板の製造方法において、前記金属被膜に
融点が400℃以下のろう材を付着させ、次いで付着した
該ろう材と前記金属ピンを軸方向に立てた下端とを接触
させて前記金属ピンに通電して加熱し、前記ろう材を溶
融させて前記金属ピン表面の成分と前記金属被膜の成分
と前記ろう材の成分とからなり再溶融温度が600℃以上
の合金層を形成し、前記金属ピンを前記金属ピンの軸方
向に加圧して前記ろう材を排除し、前記金属被膜と前記
金属ピンを前記合金層により直接接合することを特徴と
する金属ピンを有するセラミック基板の製造方法。
4. A method for manufacturing a ceramic substrate having a metal pin formed on a ceramic substrate, the metal pin being erected in the axial direction of the metal pin so as to be joined thereto, wherein a brazing material having a melting point of 400.degree. After adhering, the adhering brazing filler metal and the lower end of the metal pin standing upright in the axial direction are brought into contact with each other, and the metal pin is energized and heated to melt the brazing filler metal and the components of the metal pin surface and An alloy layer having a remelting temperature of 600 ° C. or higher formed of the components of the metal coating and the brazing filler metal is formed, and the brazing filler metal is removed by pressing the metal pin in the axial direction of the metal pin, A method for manufacturing a ceramic substrate having a metal pin, wherein the coating film and the metal pin are directly bonded by the alloy layer.
JP62174180A 1987-07-13 1987-07-13 Ceramic board having metal pins and method of manufacturing the same Expired - Lifetime JPH0783083B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62174180A JPH0783083B2 (en) 1987-07-13 1987-07-13 Ceramic board having metal pins and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62174180A JPH0783083B2 (en) 1987-07-13 1987-07-13 Ceramic board having metal pins and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPS6418245A JPS6418245A (en) 1989-01-23
JPH0783083B2 true JPH0783083B2 (en) 1995-09-06

Family

ID=15974112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62174180A Expired - Lifetime JPH0783083B2 (en) 1987-07-13 1987-07-13 Ceramic board having metal pins and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JPH0783083B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007037184A1 (en) * 2005-09-28 2007-04-05 Neomax Materials Co., Ltd. Process for producing electrode wire for solar battery

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03141662A (en) * 1989-10-26 1991-06-17 Matsushita Electric Works Ltd Manufacture of ceramic wiring circuit board
JP4953112B2 (en) * 2001-06-08 2012-06-13 東海高熱工業株式会社 Bonding structure of conductive ceramic and electrode terminal and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083356A (en) * 1983-10-14 1985-05-11 Hitachi Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007037184A1 (en) * 2005-09-28 2007-04-05 Neomax Materials Co., Ltd. Process for producing electrode wire for solar battery

Also Published As

Publication number Publication date
JPS6418245A (en) 1989-01-23

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