JP2001127375A - Submount for mounting optical semiconductor element - Google Patents

Submount for mounting optical semiconductor element

Info

Publication number
JP2001127375A
JP2001127375A JP31001899A JP31001899A JP2001127375A JP 2001127375 A JP2001127375 A JP 2001127375A JP 31001899 A JP31001899 A JP 31001899A JP 31001899 A JP31001899 A JP 31001899A JP 2001127375 A JP2001127375 A JP 2001127375A
Authority
JP
Japan
Prior art keywords
layer
optical semiconductor
semiconductor element
brazing material
submount
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31001899A
Other languages
Japanese (ja)
Inventor
Yuichiro Yamaguchi
雄一朗 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP31001899A priority Critical patent/JP2001127375A/en
Publication of JP2001127375A publication Critical patent/JP2001127375A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/0206Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0213Sapphire, quartz or diamond based substrates

Landscapes

  • Semiconductor Lasers (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a submount for mounting an optical semiconductor element which can prevent the breakage of the optical semiconductor element due to conveyance of thermal stress thereto as well as alloying of metallic layer elements in a brazing material layer when the brazing material layer is heated and melted to join the optical semiconductor element, and also prevent an increase in melting point due to compositional change of the brazing material layer. SOLUTION: This mounting electrode is formed by forming a joint layer in which a metallic layer 5 made of Au, Ag, Cu, or alloy made of these elements, a second diffusion prevention layer 6 and a brazing layer 7 are laminated in sequence, on a wiring layer in which an adhesive metallic layer 2, a diffusion prevention layer 3 and a main conductor layer 4 are laminated in sequence on the optical semiconductor element mounting part on a diamond substrate 1.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体レーザ等の
光半導体素子を搭載する光半導体素子搭載用サブマウン
ト,光半導体素子用キャリアに関し、特に高出力の半導
体レーザや精密な温度制御が必要な半導体レーザ等を搭
載するためのものに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a submount for mounting an optical semiconductor element such as a semiconductor laser and an optical semiconductor element carrier, and more particularly to a high-output semiconductor laser and a precise temperature control. The present invention relates to a device for mounting a semiconductor laser or the like.

【0002】[0002]

【従来の技術】従来の光半導体素子搭載用サブマウント
(以下、サブマウントと略す)の光半導体素子搭載用の
配線層、および光半導体素子接合用の接合層の部分断面
図を図2に示す。同図において、1は熱伝導性および強
度に優れたダイヤモンド基板、2は密着性の良好なTi
等からなる密着金属層、3は密着金属層2の成分が上側
の主導体層4に拡散するのを防止する拡散防止層(以
下、バリア層ともいう)、4はAu等からなる主導体層
であり、これらの密着金属層2,拡散防止層3,主導体
層4が配線層を構成する。そして、主導体層4上に、光
半導体電子部品等の配線層と接合するためのAu−Sn
合金等からなる低融点のロウ材層7が積層され、ロウ材
層7が接合層を構成する。なお、ダイヤモンド基板1の
1主面に配線層,接合層が積層され、他方主面にも配線
層が形成されているが、他方主面の配線層はない場合も
ある。
2. Description of the Related Art FIG. 2 is a partial cross-sectional view of a wiring layer for mounting an optical semiconductor element of a conventional submount for mounting an optical semiconductor element (hereinafter abbreviated as a submount) and a bonding layer for bonding an optical semiconductor element. . In the figure, 1 is a diamond substrate having excellent thermal conductivity and strength, and 2 is a Ti substrate having good adhesion.
3 is a diffusion prevention layer (hereinafter, also referred to as a barrier layer) for preventing components of the adhesion metal layer 2 from diffusing into the upper main conductor layer 4, and 4 is a main conductor layer made of Au or the like. The adhesion metal layer 2, the diffusion preventing layer 3, and the main conductor layer 4 constitute a wiring layer. Then, on the main conductor layer 4, Au—Sn for joining with a wiring layer of an optical semiconductor electronic component or the like.
A low melting point brazing material layer 7 made of an alloy or the like is laminated, and the brazing material layer 7 forms a bonding layer. Although a wiring layer and a bonding layer are laminated on one main surface of the diamond substrate 1 and a wiring layer is also formed on the other main surface, there may be no wiring layer on the other main surface.

【0003】このようなサブマウント用のダイヤモンド
基板1は、全体がダイヤモンドからなるもの、またはシ
リコン基板の表面にダイヤモンド膜をCVD法等により
コーティングした後、シリコン基板を溶解除去してダイ
ヤモンド膜のみを残し、このダイヤモンド膜を基板とし
たものが用いられていた(特開平6―177135号公
報,特公平7―54834号公報参照)。そして、ダイ
ヤモンド基板1の1主面上に、密着金属層としてのTi
層,拡散防止層としてのPt層,主導体層としてのAu
層を順次積層させた配線層を形成し、その配線層上に部
分的に接合層としてのAu−Sn合金半田等の金属ロウ
材を所定のパターンで形成し、さらにその接合層上にG
aAs等の半導体材料からなる半導体レーザ等を載置し
マウントして使用していた。さらに、半導体レーザを搭
載したサブマウントの他方主面(裏面)側は、Pb−S
n半田等により、Cu−W配線層上や母基板としてのセ
ラミック基板上に接合されていた。
[0003] Such a diamond substrate 1 for submount is composed entirely of diamond, or a diamond film is coated on the surface of a silicon substrate by a CVD method or the like, and then the silicon substrate is dissolved and removed to remove only the diamond film. In this case, a substrate using this diamond film as a substrate was used (see Japanese Patent Application Laid-Open No. H6-177135 and Japanese Patent Publication No. H7-54834). Then, on one main surface of the diamond substrate 1, Ti as an adhesion metal layer is formed.
Layer, Pt layer as a diffusion preventing layer, Au as a main conductor layer
A wiring layer in which layers are sequentially laminated is formed, a metal brazing material such as an Au—Sn alloy solder is partially formed on the wiring layer as a bonding layer in a predetermined pattern, and G is further formed on the bonding layer.
A semiconductor laser made of a semiconductor material such as aAs has been mounted and mounted. Further, the other main surface (back surface) side of the submount on which the semiconductor laser is mounted is Pb-S
It was bonded on the Cu-W wiring layer or the ceramic substrate as the mother substrate by n solder or the like.

【0004】配線層を構成する上記密着金属層2,拡散
防止層3,主導体層4は、スパッタリング法,蒸着法等
の薄膜形成法により形成され、フォトリソグラィ法によ
り所望のパターンに加工することで、光半導体素子搭載
用の配線層として形成される。前記配線層は、一般に、
Ti,Cr,Ta等からなる密着金属層、Pt,Pd,
Ni等からなる拡散防止層、Au等からなる主導体層を
順次積層させた3層構造からなり、特に特性的に良好な
層構成としてTi層,Pt層,Au層の層構成を採るこ
とが多い。
The above-mentioned adhesive metal layer 2, diffusion preventing layer 3, and main conductor layer 4 constituting the wiring layer are formed by a thin film forming method such as a sputtering method or a vapor deposition method, and are processed into a desired pattern by a photolithographic method. Thus, it is formed as a wiring layer for mounting the optical semiconductor element. The wiring layer generally comprises
An adhesion metal layer made of Ti, Cr, Ta, etc., Pt, Pd,
It has a three-layer structure in which a diffusion prevention layer made of Ni or the like and a main conductor layer made of Au or the like are sequentially laminated, and a layer structure of a Ti layer, a Pt layer, and an Au layer can be adopted as a particularly good layer structure. Many.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記従
来のサブマウントにおいては、ダイヤモンド基板1と搭
載する光半導体素子とは、それらの熱膨張係数差および
駆動時の温度差により熱応力が発生し、この熱応力によ
ってGaAs単結晶等の脆い化合物半導体材料から成る
半導体レーザ等が破壊されるといった問題があった。例
えば、ダイヤモンド基板1の熱膨張係数が2.3×10
6/℃程度なのに対し、GaAs単結晶から成る光半
導体素子の熱膨張係数は6.5×10 6/℃程度であ
るため、その差は4.2×10 6/℃程度となり、大
きな熱歪みが発生し、ダイヤモンド基板1と光半導体素
子との間に大きな熱応力が生じていた。
However, in the above-mentioned conventional submount, thermal stress is generated between the diamond substrate 1 and the mounted optical semiconductor element due to a difference between their thermal expansion coefficients and a temperature difference during driving. There has been a problem that a semiconductor laser or the like made of a brittle compound semiconductor material such as a GaAs single crystal is broken by the thermal stress. For example, the coefficient of thermal expansion of the diamond substrate 1 is 2.3 × 10
- to 6 / ° C. about a of the thermal expansion coefficient of the optical semiconductor element comprising a GaAs single crystal 6.5 × 10 - because it is about 6 / ° C., the difference is 4.2 × 10 - becomes 6 / ° C. approximately, Large thermal strain was generated, and large thermal stress was generated between the diamond substrate 1 and the optical semiconductor element.

【0006】また、プラズマCVD法(以下、CVD法
という)により他の基板上にダイヤモンド薄膜を形成し
たものの場合、ダイヤモンド薄膜は厚み方向に配向した
多結晶体からなる。このような配向性がある場合、引っ
張り応力や圧縮応力により破壊され易いという性質があ
る。このため、CVD法により形成されたダイヤモンド
薄膜からなるダイヤモンド基板1は、このダイヤモンド
基板1が搭載される他のセラミック基板,金属基板,ま
たはパッケージとの間の熱応力により、破壊され易いと
いう問題点もあった。
In the case where a diamond thin film is formed on another substrate by a plasma CVD method (hereinafter, referred to as a CVD method), the diamond thin film is made of a polycrystal oriented in a thickness direction. When there is such an orientation, there is a property that it is easily broken by a tensile stress or a compressive stress. For this reason, the diamond substrate 1 made of a diamond thin film formed by the CVD method is easily broken due to thermal stress between the diamond substrate 1 and another ceramic substrate, a metal substrate, or a package on which the diamond substrate 1 is mounted. There was also.

【0007】従って、本発明は上記事情に鑑みて完成さ
れたものであり、その目的は、ダイヤモンド基板と搭載
する光半導体素子との熱膨張係数差および駆動時の温度
差による熱応力によって、GaAs単結晶等の脆い化合
物半導体材料から成る半導体レーザ等が破壊されるのを
防止することにある。
Accordingly, the present invention has been completed in view of the above circumstances, and an object of the present invention is to provide a GaAs substrate having a thermal expansion coefficient difference between a diamond substrate and an optical semiconductor element mounted thereon and a thermal stress caused by a temperature difference during driving. An object of the present invention is to prevent a semiconductor laser or the like made of a brittle compound semiconductor material such as a single crystal from being broken.

【0008】[0008]

【課題を解決するための手段】本発明の光半導体素子搭
載用サブマウントは、ダイヤモンド基板上の光半導体素
子搭載部に、密着金属層と拡散防止層と主導体層とを順
次積層させた配線層上に、Au,Ag,Cuまたはこれ
らの合金から成る金属層と第2の拡散防止層とロウ材層
とを順次積層させた接合層を形成して成る搭載用電極を
設けたことを特徴とする。
A submount for mounting an optical semiconductor device according to the present invention is a wiring in which an adhesion metal layer, a diffusion prevention layer, and a main conductor layer are sequentially laminated on an optical semiconductor device mounting portion on a diamond substrate. A mounting electrode formed by forming a bonding layer in which a metal layer made of Au, Ag, Cu or an alloy thereof, a second diffusion prevention layer, and a brazing material layer are sequentially formed on the layer is provided. And

【0009】本発明は、上記構成により、ダイヤモンド
基板と搭載する光半導体素子との間に大きな熱歪みが発
生した際に、軟質の金属層が容易に変形して熱歪みによ
る熱応力を吸収する。従って、大きな熱応力が光半導体
素子側に伝わり難いため、熱応力により光半導体素子が
破損されにくくなる。また、金属層とロウ材層との間に
第2の拡散防止層が存在するので、光半導体素子を接合
するためにロウ材層を加熱溶融させた時に、金属層成分
がロウ材層中に融け込んで合金化することがなく、ロウ
材層の組成変化による融点上昇が生じず、その結果良好
な接合性が得られる。
According to the present invention, when a large thermal strain occurs between the diamond substrate and the mounted optical semiconductor element, the soft metal layer easily deforms and absorbs thermal stress due to the thermal strain. . Therefore, since a large thermal stress is hardly transmitted to the optical semiconductor element side, the optical semiconductor element is hardly damaged by the thermal stress. In addition, since the second diffusion prevention layer exists between the metal layer and the brazing material layer, when the brazing material layer is heated and melted to join the optical semiconductor elements, the metal layer component is contained in the brazing material layer. There is no melting and alloying, and no increase in the melting point due to a change in the composition of the brazing material layer. As a result, good bondability can be obtained.

【0010】[0010]

【発明の実施の形態】本発明のサブマウントについて以
下に説明する。図1は本発明のサブマウントの部分断面
図であり、1はダイヤモンド基板、2はTi,Cr,N
i−Cr,Ta等からなる密着金属層、3はPt,P
d,Ni−Cr,Ti―W等からなる拡散防止層、4は
Au等からなる主導体層、5はAu,Ag,Cuまたは
これらの合金からなる金属層、6はPt,Rh,Ru等
からなる第2の拡散防止層、7はAu−Sn合金ロウ
材,Au−Ge合金ロウ材,Pb−Sn半田,In−S
n半田等からなる光半導体素子接合用のロウ材層であ
る。これらの密着金属層2,拡散防止層3,および主導
体層4は配線層を構成し、金属層5,第2の拡散防止層
6,およびロウ材層7は光半導体素子接合用の接合層を
構成する。そして、配線層上の一部に接合層を形成して
成る光半導体素子の搭載用電極が設けられる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A submount according to the present invention will be described below. FIG. 1 is a partial cross-sectional view of a submount according to the present invention, wherein 1 is a diamond substrate, 2 is Ti, Cr, N
An adhesion metal layer made of i-Cr, Ta, etc., 3 is Pt, P
d, a diffusion preventing layer made of Ni-Cr, Ti-W, etc., 4 is a main conductor layer made of Au or the like, 5 is a metal layer made of Au, Ag, Cu or an alloy thereof, 6 is Pt, Rh, Ru, etc. A second diffusion prevention layer made of Au-Sn alloy brazing material, Au-Ge alloy brazing material, Pb-Sn solder, In-S
This is a brazing material layer made of n solder or the like for joining optical semiconductor elements. The adhesion metal layer 2, the diffusion preventing layer 3, and the main conductor layer 4 constitute a wiring layer, and the metal layer 5, the second diffusion preventing layer 6, and the brazing material layer 7 form a bonding layer for bonding an optical semiconductor element. Is configured. Then, an electrode for mounting the optical semiconductor element, which is formed by forming a bonding layer on a part of the wiring layer, is provided.

【0011】そして、これらの密着金属層2,拡散防止
層3,主導体層4,金属層5,第2の拡散防止層6,お
よびロウ材層7は、以下のようにして形成される。ま
ず、公知の2層レジスト法により、配線層が形成される
部分以外の部分にレジスト膜を形成する。その後、レジ
スト膜上の全面に密着金属層2,拡散防止層3,主導体
層4を蒸着法,スパッタリング法等の薄膜形成法により
順次積層する。成膜終了後、レジスト剥離液中にダイヤ
モンド基板1を浸漬することにより、余分なレジスト膜
をリフトオフし、所望のパターンを有する配線層が形成
される。なお、前記のリフトオフ法は、2層レジスト法
に限らず、3層レジスト法,画像反転レジスト法等によ
るものであってもよい。同様にして、配線層上に部分的
に、金属層5,第2の拡散防止層6,およびロウ材層7
からなる接合層を形成する。
The adhesion metal layer 2, diffusion prevention layer 3, main conductor layer 4, metal layer 5, second diffusion prevention layer 6, and brazing material layer 7 are formed as follows. First, a resist film is formed on a portion other than the portion where the wiring layer is formed by a known two-layer resist method. Thereafter, an adhesion metal layer 2, a diffusion preventing layer 3, and a main conductor layer 4 are sequentially laminated on the entire surface of the resist film by a thin film forming method such as an evaporation method or a sputtering method. After completion of the film formation, the excess resist film is lifted off by immersing the diamond substrate 1 in a resist stripping solution, and a wiring layer having a desired pattern is formed. The lift-off method is not limited to the two-layer resist method, but may be a three-layer resist method, an image inversion resist method, or the like. Similarly, the metal layer 5, the second diffusion prevention layer 6, and the brazing material layer 7 are partially formed on the wiring layer.
Is formed.

【0012】本発明において、密着金属層2,拡散防止
層3,主導体層4の厚さについては特に限定するもので
はないが、密着金属層2の厚さは60〜1200nm程
度であり、拡散防止層3の厚さは500〜2500nm
程度であり、主導体層4の厚さは200〜5000nm
程度である。
In the present invention, the thickness of the close contact metal layer 2, the diffusion preventing layer 3, and the main conductor layer 4 is not particularly limited, but the thickness of the close contact metal layer 2 is about 60 to 1200 nm. The thickness of the prevention layer 3 is 500 to 2500 nm.
And the thickness of the main conductor layer 4 is 200 to 5000 nm.
It is about.

【0013】また、金属層5の厚さは1.0μm以上が
良く、1.0μm未満では金属層5の熱応力吸収効果が
十分ではないため光半導体素子が破壊され易くなる。
5.0μmを超えると高コスト化するため、より好まし
くは1.0〜5.0μmがよい。第2の拡散防止層6の
厚さは0.1μm以上が良く、0.1μm未満では、十
分な拡散防止効果がないため、ロウ材層7の加熱による
接合時にロウ材層7中に金属層5成分が拡散し溶け込む
ため、ロウ材層7の融点が上昇し接合性が劣化する。
0.5μmを超えると高コスト化するため、より好まし
くは0.1〜0.5μmがよい。
The thickness of the metal layer 5 is preferably 1.0 μm or more. If the thickness is less than 1.0 μm, the effect of absorbing the thermal stress of the metal layer 5 is not sufficient, so that the optical semiconductor element is easily broken.
If the thickness exceeds 5.0 μm, the cost is increased. Therefore, the thickness is more preferably 1.0 to 5.0 μm. The thickness of the second diffusion prevention layer 6 is preferably 0.1 μm or more. If the thickness is less than 0.1 μm, there is no sufficient diffusion prevention effect. Since the five components are diffused and melted, the melting point of the brazing material layer 7 increases, and the bondability deteriorates.
If the thickness exceeds 0.5 μm, the cost is increased. Therefore, the thickness is more preferably 0.1 to 0.5 μm.

【0014】ロウ材層7の厚さは2〜10μmがよく、
2μm未満では、金属ロウ材のボリュームが小さいた
め、光半導体素子との間にボイド、即ち金属ロウ材内に
不要な空孔が発生し易い。10μmを超えるとリフトオ
フ法等によるロウ材層7のパターン形成が困難になる。
The thickness of the brazing material layer 7 is preferably 2 to 10 μm.
If the thickness is less than 2 μm, the volume of the metal brazing material is small, so that voids, that is, unnecessary vacancies in the metal brazing material are likely to be generated between the optical semiconductor elements. If it exceeds 10 μm, it becomes difficult to form a pattern of the brazing material layer 7 by a lift-off method or the like.

【0015】本発明の金属層5は、Au,Ag,Cu,
またはこれらの金属元素のうちいずれか2種以上の合金
から成り、これらの金属元素および合金は300〜40
0MPa(メガパスカル)の最大引張応力に対して破断
時の伸び率が30%以上である軟質の金属であり、薄膜
形成した後に酸素等と反応し難く化学的安定性に優れ
る。他のSn,In等の軟質の金属は融点が低すぎ、ま
たNi等は薄膜形成後に硬化するといった特性があるた
め、上記本発明の材料とする。
The metal layer 5 of the present invention is made of Au, Ag, Cu,
Or, it is composed of an alloy of any two or more of these metal elements, and these metal elements and alloys are 300 to 40.
It is a soft metal having an elongation at break of 30% or more with respect to the maximum tensile stress of 0 MPa (megapascal). It is difficult to react with oxygen or the like after forming a thin film and has excellent chemical stability. Other soft metals such as Sn and In have melting points that are too low, and Ni and the like harden after forming a thin film.

【0016】また本発明のロウ材層7は低融点(130
〜450℃)のものがよく、加熱時間を短くして主導体
層4との反応が生じ難いものとなる。
The brazing material layer 7 of the present invention has a low melting point (130
To 450 ° C.), and the reaction time with the main conductor layer 4 hardly occurs by shortening the heating time.

【0017】ここで、サブマウントの配線層および接合
層上に半導体レーザ8を搭載した状態を図3,図4に示
す。これらの図において、8は半導体レーザ、8aは半
導体レーザ8下面の接合用のバックメタル層、8bは駆
動信号等の入力用の入力配線層、8cは発光部である。
なお、図4において、10は光半導体素子搭載部、11
は搭載用電極である。
FIGS. 3 and 4 show a state where the semiconductor laser 8 is mounted on the wiring layer and the bonding layer of the submount. In these figures, reference numeral 8 denotes a semiconductor laser, 8a denotes a back metal layer for bonding on the lower surface of the semiconductor laser 8, 8b denotes an input wiring layer for inputting drive signals and the like, and 8c denotes a light emitting unit.
In FIG. 4, reference numeral 10 denotes an optical semiconductor element mounting portion;
Is a mounting electrode.

【0018】本発明のサブマウントは、図3および図4
に示したような半導体レーザ8等の光半導体素子用のサ
ブマウントに限らず、LSI,IC等を搭載するサブマ
ウントおよび配線基板にも適用できることはいうまでも
ない。また、本発明の配線層は、図3,図4に示すよう
に、その上に接合層を介して光半導体素子の電極等が載
置接合されるものであるが、配線層はより複雑なパター
ンを形成してもよい。さらに、本発明のサブマウントは
GaAs等の脆い半導体材料からなる光半導体素子用と
して好適なものであるが、GaAs以外の半導体材料か
らなる光半導体素子にも適用できることはいうまでもな
い。
FIGS. 3 and 4 show the submount of the present invention.
It goes without saying that the present invention can be applied not only to the submount for an optical semiconductor device such as the semiconductor laser 8 as described in the above, but also to a submount and a wiring board on which an LSI, an IC, etc. are mounted. Further, as shown in FIGS. 3 and 4, the wiring layer of the present invention has an electrode and the like of an optical semiconductor element placed and bonded thereon via a bonding layer, but the wiring layer is more complicated. A pattern may be formed. Furthermore, the submount of the present invention is suitable for an optical semiconductor device made of a brittle semiconductor material such as GaAs, but it goes without saying that the submount can be applied to an optical semiconductor device made of a semiconductor material other than GaAs.

【0019】かくして、本発明は、ダイヤモンド基板と
搭載する光半導体素子との間に大きな熱歪みが発生した
際に、金属層が容易に変形して熱歪みによる熱応力を吸
収し、熱応力により光半導体素子が破損されにくくな
る。また、光半導体素子を接合するためにロウ材層を加
熱溶融させた時に、金属層成分がロウ材層中に融け込ん
で合金化することがなく、ロウ材層の組成変化による融
点上昇が生じず、その結果良好な接合性が得られるとい
う作用効果を有する。
Thus, according to the present invention, when a large thermal strain occurs between the diamond substrate and the mounted optical semiconductor element, the metal layer is easily deformed to absorb the thermal stress caused by the thermal strain, and The optical semiconductor element is less likely to be damaged. In addition, when the brazing material layer is heated and melted to join the optical semiconductor elements, the metal layer component does not melt into the brazing material layer to form an alloy, and the melting point rises due to a change in the composition of the brazing material layer. However, as a result, there is an operational effect that good bonding properties can be obtained.

【0020】なお、本発明は上記実施形態に限定される
ものではなく、本発明の要旨を逸脱しない範囲内におい
て種々の変更を行なうことは何等差し支えない。
It should be noted that the present invention is not limited to the above embodiment, and that various changes may be made without departing from the spirit of the present invention.

【0021】[0021]

【実施例】本発明の実施例を以下に説明する。Embodiments of the present invention will be described below.

【0022】(実施例)図1のサブマウントを以下のよ
うにして構成した。シリコン基板上に、CVD法により
厚さ300μmのダイヤモンド膜を成膜し、シリコン基
板を水酸化カリウム液により溶解して除去し、ダイヤモ
ンド膜を基板とした。このダイヤモンド基板から個々の
ダイヤモンド基板1を切り出し、2mm角のダイヤモン
ド基板1を作製した。
(Example) The submount of FIG. 1 was constructed as follows. A diamond film having a thickness of 300 μm was formed on a silicon substrate by a CVD method, and the silicon substrate was dissolved and removed with a potassium hydroxide solution to obtain a diamond film. Each diamond substrate 1 was cut out from the diamond substrate to produce a 2 mm square diamond substrate 1.

【0023】このダイヤモンド基板1の一方の主面に、
2層レジスト法により配線層が形成される部分以外の部
分にレジスト膜を形成し、2層レジスト法によりパター
ン形成した後、この主面の全面に厚さ0.1μmのTi
からなる密着金属層2、厚さ0.1μmのPtからなる
拡散防止層3、厚さ1.0μmのAuからなる主導体層
を、スパッタリング法により順次積層させた。次いで、
レジスト層を剥離除去して、所望のパターンとなるよう
にパターン加工した。
On one main surface of the diamond substrate 1,
A resist film is formed in a portion other than the portion where the wiring layer is to be formed by the two-layer resist method, and a pattern is formed by the two-layer resist method.
, A diffusion preventing layer 3 made of Pt having a thickness of 0.1 μm, and a main conductor layer made of Au having a thickness of 1.0 μm were sequentially laminated by a sputtering method. Then
The resist layer was stripped and removed, and pattern processing was performed to obtain a desired pattern.

【0024】同様にして、配線層上に部分的に、2層レ
ジスト法,スパッタリング法により、表1に示すように
種々の厚さおよび組成の金属層5,種々の厚さおよび組
成の第2の拡散防止層6,Au−Sn合金半田(融点2
80℃)のロウ材層7を順次積層させ、リフトオフする
ことにより、所望のパターンとなるようにパターン加工
した。このロウ材層7上に、1mm×1mm×0.1m
mのGaAsを半導体材料とする半導体レーザを下記の
ように接合搭載し、温度サイクル試験による熱応力破壊
テスト、半田濡れ性の評価を行い、その結果を表1に示
す。
Similarly, as shown in Table 1, metal layers 5 of various thicknesses and compositions and second layers of various thicknesses and compositions were partially formed on the wiring layer by a two-layer resist method and a sputtering method. Diffusion prevention layer 6, Au-Sn alloy solder (melting point 2
(80 ° C.) were sequentially laminated, and lift-off was performed to perform pattern processing to obtain a desired pattern. 1 mm × 1 mm × 0.1 m on this brazing material layer 7
A semiconductor laser using GaAs of m as a semiconductor material was bonded and mounted as described below, and a thermal stress breakdown test by a temperature cycle test and an evaluation of solder wettability were performed. The results are shown in Table 1.

【0025】[0025]

【表1】 [Table 1]

【0026】表1において、熱応力破壊テスト(熱応力
特性試験)、半田濡れ性の評価は以下のように行った。
ロウ材層7の融点より20〜50℃程度高い温度に保持
したヒータブロック上にサブマウントを載置し、その1
0秒後に、接合用のバックメタル層として厚さ0.1μ
mのTi層,厚さ0.1μmのPt層,厚さ0.1μm
のAu層を順次積層させた半導体レーザをサブマウント
の接合層上に載置した。1秒間その状態を維持した後、
2秒間半導体レーザをスクラブして金属ロウ材をよくな
じませた後、ヒータブロックから半導体レーザを外し、
常温まで冷却した。
In Table 1, the thermal stress fracture test (thermal stress characteristic test) and the evaluation of solder wettability were performed as follows.
The submount is mounted on a heater block which is maintained at a temperature about 20 to 50 ° C. higher than the melting point of the brazing material layer 7.
After 0 seconds, a thickness of 0.1 μm
m Ti layer, 0.1 μm thick Pt layer, 0.1 μm thick
Was mounted on the bonding layer of the submount. After maintaining that state for one second,
After scrubbing the semiconductor laser for 2 seconds to allow the metal brazing material to spread well, remove the semiconductor laser from the heater block,
Cooled to room temperature.

【0027】そして、同種の各10個のサンプルについ
て上記温度サイクル試験を行った。その条件は、―40
℃から85℃まで10分で昇温させ、85℃を20分維
持し、85℃から―40℃まで10分で降温させ、―4
0℃を20分維持するのを1サイクルとし、これを10
00サイクル行った。温度サイクル試験後、半導体レー
ザの破壊の有無を観察し、破壊がなければ適、破壊があ
れば不適とした。
Then, the above-mentioned temperature cycle test was performed on ten samples of the same kind. The condition is -40
The temperature was raised from 85 ° C. to 85 ° C. in 10 minutes, the temperature was maintained at 85 ° C. for 20 minutes, and the temperature was lowered from 85 ° C. to −40 ° C. in 10 minutes.
Maintaining 0 ° C. for 20 minutes is defined as one cycle,
00 cycles were performed. After the temperature cycle test, the presence or absence of breakage of the semiconductor laser was observed.

【0028】また、340℃に加熱したヒータブロック
上に1個のサンプルを載置し、120秒間ロウ材層7の
融解状態を観察し、半田濡れ性の評価を行った。120
秒後でも半田が融解していたものを2重丸印、60秒以
上融解していたものを丸印、20秒以上融解していたも
のを三角印、20秒未満で固化したものをばつ印とし
た。なお、表1において、バリアメタルは第2の拡散防
止層6を意味する。
One sample was placed on a heater block heated to 340 ° C., and the melting state of the brazing material layer 7 was observed for 120 seconds to evaluate solder wettability. 120
A double circle indicates that the solder was melted even after 2 seconds, a circle indicates that the solder was melted for 60 seconds or more, a triangle indicates that the solder was melted for 20 seconds or more, and a cross indicates that the solidified in less than 20 seconds. And In Table 1, the barrier metal means the second diffusion prevention layer 6.

【0029】表1より、NO.1〜4,17,19,2
1,23では、金属層5の厚さが0.5μmであり、そ
のため半導体レーザが温度サイクルテストで破壊され不
適となった。一方、NO.5〜16のように金属層5の
厚さが1.0μm以上の場合、半導体レーザが温度サイ
クルテストで破壊されなかった。よって、金属層5の厚
さは1.0μm以上がよいことが判った。また、バリア
メタルの厚さにより半田濡れ性は変化し、その厚さが
0.1μm以上のとき良好な結果を示した。なお、A
u,Ag,Cuのうちいずれか2種以上の合金について
も同じように調べた結果、同様の特性が得られた。
As shown in Table 1, NO. 1-4, 17, 19, 2
In Nos. 1 and 23, the thickness of the metal layer 5 was 0.5 μm, so that the semiconductor laser was destroyed in the temperature cycle test and became unsuitable. On the other hand, NO. When the thickness of the metal layer 5 was 1.0 μm or more as in 5 to 16, the semiconductor laser was not broken in the temperature cycle test. Therefore, it was found that the thickness of the metal layer 5 was preferably 1.0 μm or more. In addition, the solder wettability changed depending on the thickness of the barrier metal, and good results were shown when the thickness was 0.1 μm or more. Note that A
Similar properties were obtained as a result of the same examination for any two or more alloys of u, Ag, and Cu.

【0030】そして、比較例として、金属層5およびバ
リアメタルの両方がない場合(NO.33)、バリアメ
タルをNiとした場合(NO.34)、バリアメタルが
ない場合(NO.35)の3種について、上記と同様に
温度サイクルテストおよび半田濡れ性評価を行った結果
を表2に示す。
As a comparative example, when there is no metal layer 5 and no barrier metal (NO. 33), when the barrier metal is Ni (NO. 34), and when there is no barrier metal (NO. 35), Table 2 shows the results of the temperature cycle test and the evaluation of the solder wettability for the three types in the same manner as described above.

【0031】[0031]

【表2】 [Table 2]

【0032】表2より、NO.33では、金属層5がな
いので温度サイクルテストは不適であったが、下地のP
t層の影響で半田濡れ性は良好であった。NO.34で
は、温度サイクルテストは適であり、これはバリアメタ
ルの存在が有効なことを示しているが、半田濡れ性は不
良であった。これは、バリアメタル材料としてNiが不
適であることを示している。また、NO.35では、金
属層5成分とロウ材層7成分の合金化が生じるため、温
度サイクルテスト時に金属層5が硬化して不適となり、
ロウ材層7の融点上昇と組成の非共晶点化のため、半田
濡れ性が不良となった。
From Table 2, it can be seen that NO. In No. 33, the temperature cycle test was unsuitable because the metal layer 5 was not provided.
Solder wettability was good under the influence of the t layer. NO. In No. 34, the temperature cycle test was suitable, indicating that the presence of the barrier metal was effective, but the solder wettability was poor. This indicates that Ni is not suitable as a barrier metal material. In addition, NO. In 35, since the metal layer 5 component and the brazing material layer 7 component are alloyed, the metal layer 5 hardens during the temperature cycle test and becomes unsuitable.
The solder wettability was poor due to the rise in the melting point of the brazing material layer 7 and the non-eutectic point of the composition.

【0033】[0033]

【発明の効果】本発明は、ダイヤモンド基板上の光半導
体素子搭載部に、密着金属層と拡散防止層と主導体層と
を順次積層させた配線層上に、Au,Ag,Cuまたは
これらの合金から成る金属層と第2の拡散防止層とロウ
材層とを順次積層させた接合層を形成して成る搭載用電
極を設けたことにより、ダイヤモンド基板と光半導体素
子との間に大きな熱歪みが発生した際に、金属層が容易
に変形して熱歪みによる熱応力を吸収し、大きな熱応力
が光半導体素子側に伝わり難いため、光半導体素子が破
損されにくくなる。また、金属層とロウ材層との間に第
2の拡散防止層が存在するので、光半導体素子を接合す
るためにロウ材層を加熱溶融させた時に、金属層成分が
ロウ材層中に融け込んで合金化することがなく、ロウ材
層の組成変化による融点上昇が生じず、その結果良好な
接合性が得られる。
According to the present invention, Au, Ag, Cu or any of these is formed on a wiring layer in which an adhesion metal layer, a diffusion prevention layer, and a main conductor layer are sequentially laminated on an optical semiconductor element mounting portion on a diamond substrate. By providing a mounting electrode formed by forming a bonding layer in which a metal layer made of an alloy, a second diffusion prevention layer, and a brazing material layer are sequentially laminated, a large heat is generated between the diamond substrate and the optical semiconductor element. When distortion occurs, the metal layer is easily deformed, absorbs thermal stress due to thermal strain, and it is difficult for the large thermal stress to be transmitted to the optical semiconductor element side, so that the optical semiconductor element is less likely to be damaged. In addition, since the second diffusion prevention layer exists between the metal layer and the brazing material layer, when the brazing material layer is heated and melted to join the optical semiconductor elements, the metal layer component is contained in the brazing material layer. There is no melting and alloying, and no increase in the melting point due to a change in the composition of the brazing material layer. As a result, good bondability can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の光半導体素子搭載用サブマウントの配
線層および接合層の部分断面図である。
FIG. 1 is a partial cross-sectional view of a wiring layer and a bonding layer of a submount for mounting an optical semiconductor element of the present invention.

【図2】従来の光半導体素子搭載用サブマウントの配線
層および接合層の部分断面図である。
FIG. 2 is a partial sectional view of a wiring layer and a bonding layer of a conventional optical semiconductor element mounting submount.

【図3】半導体レーザを搭載した本発明の光半導体素子
搭載用サブマウントの配線層および接合層の部分断面図
である。
FIG. 3 is a partial sectional view of a wiring layer and a bonding layer of a submount for mounting an optical semiconductor element of the present invention on which a semiconductor laser is mounted.

【図4】半導体レーザを搭載した本発明の光半導体素子
搭載用サブマウントの平面図である。
FIG. 4 is a plan view of an optical semiconductor element mounting submount of the present invention on which a semiconductor laser is mounted.

【符号の説明】[Explanation of symbols]

1:ダイヤモンド基板 2:密着金属層 3:拡散防止層 4:主導体層 5:金属層 6:第2の拡散防止層 7:ロウ材層 8:半導体レーザ 1: Diamond substrate 2: Adhesive metal layer 3: Diffusion prevention layer 4: Main conductor layer 5: Metal layer 6: Second diffusion prevention layer 7: Brazing material layer 8: Semiconductor laser

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】ダイヤモンド基板上の光半導体素子搭載部
に、密着金属層と拡散防止層と主導体層とを順次積層さ
せた配線層上に、Au,Ag,Cuまたはこれらの合金
から成る金属層と第2の拡散防止層とロウ材層とを順次
積層させた接合層を形成して成る搭載用電極を設けたこ
とを特徴とする光半導体素子搭載用サブマウント。
1. A metal layer made of Au, Ag, Cu or an alloy thereof on a wiring layer in which an adhesion metal layer, a diffusion preventing layer and a main conductor layer are sequentially laminated on an optical semiconductor element mounting portion on a diamond substrate. A submount for mounting an optical semiconductor element, comprising: a mounting electrode formed by forming a bonding layer in which a layer, a second diffusion prevention layer, and a brazing material layer are sequentially laminated.
JP31001899A 1999-10-29 1999-10-29 Submount for mounting optical semiconductor element Pending JP2001127375A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31001899A JP2001127375A (en) 1999-10-29 1999-10-29 Submount for mounting optical semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31001899A JP2001127375A (en) 1999-10-29 1999-10-29 Submount for mounting optical semiconductor element

Publications (1)

Publication Number Publication Date
JP2001127375A true JP2001127375A (en) 2001-05-11

Family

ID=18000178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31001899A Pending JP2001127375A (en) 1999-10-29 1999-10-29 Submount for mounting optical semiconductor element

Country Status (1)

Country Link
JP (1) JP2001127375A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002103787A1 (en) * 2001-06-14 2002-12-27 Tokuyama Corporation Substrate for use in joining element
US7075960B2 (en) 2003-01-10 2006-07-11 Matsushita Electric Industrial Co., Ltd. Semiconductor laser apparatus and production method thereof
EP1695382A1 (en) * 2001-05-24 2006-08-30 Fry's Metals Inc. Thermal interface material and solder preforms
JP2006286958A (en) * 2005-03-31 2006-10-19 Toshiba Corp Ceramics wiring board and semiconductor device using same
CN100423217C (en) * 2003-08-26 2008-10-01 德山株式会社 Substrate for device bonding, device bonded substrate, and method for producing same
KR100919170B1 (en) * 2004-03-24 2009-09-28 가부시끼가이샤 도꾸야마 Substrate for device bonding and method for manufacturing same
US7663242B2 (en) 2001-05-24 2010-02-16 Lewis Brian G Thermal interface material and solder preforms
JP2013225654A (en) * 2012-03-22 2013-10-31 Nichia Chem Ind Ltd Semiconductor laser device
US9194189B2 (en) 2011-09-19 2015-11-24 Baker Hughes Incorporated Methods of forming a cutting element for an earth-boring tool, a related cutting element, and an earth-boring tool including such a cutting element
WO2018016164A1 (en) * 2016-07-22 2018-01-25 ソニーセミコンダクタソリューションズ株式会社 Element structure body and light emitting device

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1695382A1 (en) * 2001-05-24 2006-08-30 Fry's Metals Inc. Thermal interface material and solder preforms
US7663242B2 (en) 2001-05-24 2010-02-16 Lewis Brian G Thermal interface material and solder preforms
EP1695382A4 (en) * 2001-05-24 2007-10-10 Fry Metals Inc Thermal interface material and solder preforms
WO2002103787A1 (en) * 2001-06-14 2002-12-27 Tokuyama Corporation Substrate for use in joining element
CN1316605C (en) * 2001-06-14 2007-05-16 株式会社德山 Substrate for use in joining element
US7075960B2 (en) 2003-01-10 2006-07-11 Matsushita Electric Industrial Co., Ltd. Semiconductor laser apparatus and production method thereof
US7362785B2 (en) 2003-01-10 2008-04-22 Matsushita Electric Industrial Co., Ltd. Semiconductor laser apparatus and production method thereof
CN100423217C (en) * 2003-08-26 2008-10-01 德山株式会社 Substrate for device bonding, device bonded substrate, and method for producing same
KR100919170B1 (en) * 2004-03-24 2009-09-28 가부시끼가이샤 도꾸야마 Substrate for device bonding and method for manufacturing same
JP2006286958A (en) * 2005-03-31 2006-10-19 Toshiba Corp Ceramics wiring board and semiconductor device using same
JP4537877B2 (en) * 2005-03-31 2010-09-08 株式会社東芝 Ceramic circuit board and semiconductor device using the same
US9194189B2 (en) 2011-09-19 2015-11-24 Baker Hughes Incorporated Methods of forming a cutting element for an earth-boring tool, a related cutting element, and an earth-boring tool including such a cutting element
US9771497B2 (en) 2011-09-19 2017-09-26 Baker Hughes, A Ge Company, Llc Methods of forming earth-boring tools
JP2013225654A (en) * 2012-03-22 2013-10-31 Nichia Chem Ind Ltd Semiconductor laser device
WO2018016164A1 (en) * 2016-07-22 2018-01-25 ソニーセミコンダクタソリューションズ株式会社 Element structure body and light emitting device
JPWO2018016164A1 (en) * 2016-07-22 2019-05-16 ソニーセミコンダクタソリューションズ株式会社 Element structure and light emitting device
US11418004B2 (en) 2016-07-22 2022-08-16 Sony Semiconductor Solutions Corporation Element structure and light-emitting device

Similar Documents

Publication Publication Date Title
KR100940164B1 (en) Submount and semiconductor device
JP2983486B2 (en) Semiconductor substrate having a brazing material layer
WO2004015756A1 (en) Submount and semiconductor device
WO2006098454A1 (en) Submount and method for manufacturing same
JP5120653B2 (en) Solder layer, device bonding substrate using the same, and method for manufacturing the device bonding substrate
JP2009290007A (en) Jointed body, semiconductor device and method for manufacturing jointed body
CN111344844B (en) Solder joint and method for forming solder joint
TWI312647B (en)
JP2001127375A (en) Submount for mounting optical semiconductor element
EP1939929B1 (en) Heat sink using a solder layer and method for manufacturing such heat sink
JPH08255973A (en) Ceramic circuit board
JP2005032834A (en) Joining method of semiconductor chip and substrate
JP5526336B2 (en) Solder layer, device bonding substrate using the same, and manufacturing method thereof
JPH05218229A (en) Ceramic circuit board
JPH06125026A (en) Terminal structure and input-output terminal member and wiring board using it
JP3912130B2 (en) Submount
US6742248B2 (en) Method of forming a soldered electrical connection
WO2003069743A1 (en) Sub-mount and semiconductor device
JPH08102570A (en) Ceramic circuit board
JP5399953B2 (en) Semiconductor element, semiconductor device using the same, and method for manufacturing semiconductor device
JP4910789B2 (en) Power element mounting substrate, power element mounting substrate manufacturing method, and power module
JP2007109829A (en) Solder joint forming method
WO2001076335A1 (en) Mounting structure of electronic device and method of mounting electronic device
JPH0786444A (en) Manufacture of compound heat dissipating substrate for semiconductor
JPH038346A (en) Brazing material