JP4537877B2 - Ceramic circuit board and semiconductor device using the same - Google Patents

Description

  The present invention relates to a ceramic wiring board used as a semiconductor element mounting board and the like and a semiconductor device using the same.

  An insulating ceramic substrate such as an aluminum nitride substrate or a silicon nitride substrate is used as a mounting substrate for various semiconductor elements such as an optical semiconductor element such as a laser diode or a photodiode. When a ceramic substrate is applied to a submount substrate of an optical semiconductor element, a wiring layer is formed on the surface by applying a thin film forming technique such as a vacuum deposition method or a PVD method such as a sputtering method, or a CVD method. (For example, refer to Patent Document 1).

  FIG. 4 is a cross-sectional view showing the structure of a conventional ceramic wiring board. In the figure, reference numeral 1 denotes an insulating ceramic substrate made of, for example, an aluminum nitride sintered body. The surface of the insulating substrate is Au via a base metal layer 2 made of Ti or the like and a first diffusion prevention layer 3 made of Pt or the like. A main conductor layer 4 is formed. A solder layer 6 made of an Au—Sn alloy or the like is formed on a connection portion (electrode connection portion) of the main conductor layer 4 with the semiconductor element via a second diffusion prevention layer 5 made of Pt or the like. The surface of the solder layer 6 may be covered with an Au layer 7 to prevent oxidation.

  In the ceramic wiring substrate shown in FIG. 4, a conductor layer in which a base metal layer 2, a first diffusion prevention layer 3, and an Au layer (main conductor layer) 4 are sequentially laminated on the lower surface side of the insulating ceramic substrate 1. Is provided. The conductor layer on the lower surface side may be used as a bonding metal layer when the insulating ceramic substrate 1 is disposed and fixed on an external circuit board or in a package, or may be used as a ground conductor layer or the like.

The second diffusion prevention layer 5 interposed between the main conductor layer 4 and the solder layer 6 described above is used when the semiconductor element is bonded and fixed via the Au—Sn alloy or the like of the solder layer 6. 4 Au is prevented from diffusing into the solder layer 6 made of Au—Sn alloy or the like. This is because if the Au of the main conductor layer 4 diffuses into the Au—Sn solder alloy of the solder layer 6, the alloy composition becomes excessively Au (Au rich), leading to an increase in melting point and the soldering temperature (heating) of the Au—Sn alloy. (Temperature) cannot be completely melted, resulting in a decrease in bonding strength.
JP 2002-252316 A

  However, in the conventional ceramic wiring board, the bonding temperature of the Au—Sn alloy solder (the bonding temperature at the time of mounting the semiconductor element) is required to be 300 ° C. or higher, so that a thermal stress is applied to the semiconductor element in the cooling process after bonding, For example, in the case of a laser diode, dark regions and dark lines in the light emitting region have been introduced, causing problems such as deterioration in long-term reliability and defective light emission.

In order to lower the bonding temperature of the Sn alloy solder, it is conceivable to use Sn-based solder containing Ti, Ag, Cu, Bi or the like in Sn. Since the joining temperature of the Sn-based solder containing at least one of Ti, Ag, Cu, Bi, etc. is as low as 250 ° C. or less, the thermal stress in the cooling process after joining the semiconductor elements can be reduced.
However, the Sn-based solder reacts (alloys) with Ti, Ag, Cu, Bi, etc. due to heat at the time of mounting the semiconductor element, and the Sn alloy becomes a large lump in the Sn solder layer. If a large mass of Sn alloy is present in the Sn solder layer, cracks enter the interface between the Sn and Sn alloy mass due to the difference in thermal expansion between Sn and Sn alloy during the cooling process, and the electrical characteristics of the wiring layer deteriorate. For example, if there is a crack in the wiring layer of the wiring board on which the laser diode is mounted, the crack at the interface between Sn and Sn alloy develops due to the heat generated when the laser diode emits light (the crack becomes larger). When the crack progresses, the conductivity of the wiring layer is lowered, so that the threshold current when laser light is emitted gradually increases, and finally there is a problem that light is not emitted.

  The present invention has been made to cope with such problems, and suppresses the generation of Sn alloy lumps in the Sn solder layer when a semiconductor element or the like is bonded and mounted on the ceramic wiring board via the solder layer. Accordingly, an object of the present invention is to provide a ceramic wiring board that can prevent cracks in the wiring layer and the like, and a semiconductor device using the same.

The ceramic wiring board according to the present invention has a base metal layer, a first diffusion prevention layer, a conductor layer, a second diffusion prevention layer, and a layer mainly comprising at least one of Ti, Ag, Cu, and Bi on the upper surface of the ceramic substrate. And a wiring layer in which a solder layer made of Au or Au—Sn alloy layer and Sn or Sn alloy is sequentially laminated.
The Au or Au—Sn alloy layer preferably has a thickness of 0.05 μm or more and 0.5 μm or less. The Au—Sn alloy preferably contains 63% or more of Au.
The first diffusion preventing layer and the second diffusion preventing layer are preferably made of at least one of Pt, Pd, and Ni or an alloy based on them.
The Sn alloy preferably has an Sn content of 90 wt% or more. The Sn alloy is preferably an Sn alloy containing at least one selected from Au, Ag, Al, Bi, Cu, Cr, Ga, Ge, Ni, Pt, Si, Ti, and Zn.
Moreover, it is preferable that the solder layer has a structure including two or more layers of Sn alloys having different compositions.
Moreover, it is preferable that the layer mainly containing at least one of Ti, Ag, Cu, and Bi has a two-layer structure of a Ti layer and a layer mainly containing at least one of Ag, Cu, and Bi.

  The ceramic wiring board having such a configuration can be used in a semiconductor device by mounting a semiconductor element through the solder layer. The semiconductor element is an optical semiconductor element.

  In the ceramic wiring board of the present invention, the upper surface of the ceramic substrate is mainly composed of at least one of a base metal layer, a first diffusion prevention layer, a conductor layer, a second diffusion prevention layer, Ti, Ag, Cu, and Bi. Since a wiring layer in which a layer, an Au or Au—Sn alloy layer, and a solder layer made of Sn or Sn alloy are sequentially laminated is provided, the bondability (adhesiveness and bonding strength) to the semiconductor element is good. Therefore, it is possible to provide a semiconductor device with excellent reproducibility and operational characteristics with high reproducibility.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the following, embodiments of the present invention will be described with reference to the drawings. However, the drawings are provided for the purpose of illustration only, and the present invention is not limited to the drawings.

FIG. 1 is a cross-sectional view showing a main configuration of a ceramic wiring board according to an embodiment of the present invention.
The ceramic wiring substrate shown in FIG. 1 has a ceramic substrate 1 as an insulating substrate. The ceramic substrate 1 includes, for example, a nitride-based ceramic (sintered body) mainly composed of aluminum nitride (AlN), silicon nitride (Si ₃ N ₄ ), or the like, or mainly composed of aluminum oxide (Al ₂ O ₃ ) or the like. An oxide ceramic (sintered body) is used. Of these, nitride ceramics are preferably applied because of their excellent thermal conductivity. From the viewpoint of thermal conductivity, silicon carbide (SiC) is also suitable for the substrate. In addition, since silicon carbide has semiconductivity, it can be used as a wiring board by providing an insulating film on the surface.

  On the main surface of the ceramic substrate 1 as described above, for example, a vacuum deposition method, a sputtering method, an ion plating method, a molecular beam epitaxy (MBE) method, a laser deposition method, a PVD method such as an ion beam deposition method. The wiring layer 12 is formed by a thin film forming method such as a CVD method such as a thermal CVD method, a plasma CVD method or a photo CVD method, or a plating method, or by applying a solder material. The wiring layer 12 has a wiring part 13 and a connection part 14. The wiring portion 13 includes a base metal layer 2, a first diffusion prevention layer 3, and a conductor layer 4 that are sequentially stacked on the ceramic substrate 1. The conductor layer 4 is preferably a layer made of Au or an Au alloy.

  The base metal layer 2 contributes to improvement in adhesion and adhesion strength between the ceramic substrate 1 and the wiring layer 12, for example, at least one selected from Ti, Zr, Hf, Nb, Cr, Ta and Ni. Alloys based on these are used. Of these, when a nitride ceramic is applied to the ceramic substrate 1, it is preferable to apply an active metal such as Ti, Zr, Hf, or Nb. The thickness of the base metal layer 2 is not particularly limited, but is preferably in the range of 0.1 to 0.4 μm, for example.

  The first diffusion prevention layer 3 prevents diffusion of elements between the ceramic substrate 1 or the base metal layer 2 and the conductor layer 4. For example, at least one selected from Pt, Pd and Ni, or these may be used. A base alloy is used. The thickness of the first diffusion preventing layer 3 is preferably in the range of 0.05 to 0.4 μm, for example. If the thickness is less than 0.05 μm, the diffusion preventing effect may not be sufficiently obtained. On the other hand, if the thickness exceeds 0.4 μm, not only a further diffusion preventing effect cannot be obtained, but also the cost increases. The conductor layer 4 functions as the main conductor layer of the wiring part 13, and the thickness thereof is preferably in the range of 0.1 to 0.3 μm, for example. The wiring part 13 has a wiring pattern according to a desired circuit shape or the like.

  A connecting portion 14 having a solder layer 10 is provided at a position where the wiring portion 13 is connected to the semiconductor element. The connecting portion 14 is provided in a desired shape at a position corresponding to the electrode of the semiconductor element bonded and mounted on the ceramic wiring substrate, and has a function of electrically and mechanically connecting the wiring portion 13 and the semiconductor element. Is. The connection portion 14 has a shape corresponding to the electrode of the semiconductor element, for example, a shape such as a rectangle or a circle, and the size is also the same. Such a connection portion 14 includes a second diffusion prevention layer 5 that is sequentially stacked at a desired position on the wiring portion 13, a layer 8 that contains at least one of Ti, Ag, Cu, and Bi as a main component, Au Or it has the layer 9 which consists of Au-Sn alloy, and the solder layer 10 which consists of Sn or Sn alloy.

  The solder layer 10 is made of Sn or Sn alloy. For such a solder layer 10, Sn alone or Sn alloy containing at least one selected from Au, Ag, Al, Bi, Cu, Cr, Ga, Ge, Ni, Pt, Si, Ti and Zn is used. . Of these, the solder layer 10 is preferably composed of the above-described Sn alloy. The amount of Sn in the Sn alloy is appropriately selected according to the type of elements used in combination, and is preferably in the range of 15 to 99.9% by mass, for example. Typical examples of such an Sn alloy (solder alloy) include an Au—Sn alloy, an Ag—Sn alloy, a Cu—Sn alloy, and the like. In particular, an Sn alloy having an Sn content of 90% by mass or more is preferable. . It is preferable that the Sn amount be 90% by mass or more because the bonding temperature can be 250 ° C. or less. The thickness of the solder layer 10 is preferably in the range of 1 to 5 μm, for example. If the thickness of the solder layer 10 is less than 1 μm, it will react with the Au film provided on the electrode of the semiconductor element when it is bonded to the semiconductor element (the solder layer and the Au film are mixed), and composition deviation will easily occur. As a result of the composition shift, the bonding layer is hardened and stress is generated, which easily causes a defect such as a crack in a semiconductor element (for example, a laser diode). On the other hand, if the thickness exceeds 5 μm, not only a further bonding effect cannot be obtained, but also the cost increases.

  The solder layer 10 described above is not limited to one formed of one type of Sn alloy, and may be formed of a laminated film of two or more types of Sn alloys having different compositions, for example. In this case, the applied Sn alloy is not limited to two or more kinds of Sn alloys having different constituent elements, but may be two or more kinds of Sn alloys having different composition ratios of the same constituent elements. For example, the molten state of the solder layer 10 can be controlled by forming the solder layer 10 with a laminated film of two or more kinds of Au—Sn alloys having different composition ratios, that is, Au—Sn alloys having different melting temperatures.

Further, there is a layer 9 made of Au or Au—Sn alloy below the solder layer 10. The layer 9 made of Au or Au—Sn alloy is formed between the solder layer 10 and the layer 8 containing at least one of Ti, Ag, Cu, and Bi as a main component. The layer 9 made of Au or Au—Sn alloy reacts with the layer 8 mainly composed of at least one of Ti, Ag, Cu, and Bi by heating at the time of mounting the semiconductor element, and the Sn alloy is large. The generation of lumps can be suppressed.
The layer 9 made of Au or Au—Sn alloy is preferably an Au—Sn alloy layer, more preferably an Au—Sn alloy containing 63 mass% or more of Au. When Au is 63 mass% or more, the effect of suppressing the formation of a large lump made of an alloy of at least one of Ti, Ag, Cu, and Bi and Sn is enhanced.

Next, under the layer 9 made of Au or Au—Sn alloy, there is a layer 8 whose main component is at least one of Ti, Ag, Cu, and Bi. The layer 8 mainly composed of at least one of Ti, Ag, Cu, and Bi may be a layer composed of one kind of each element, or may be an alloy layer mainly composed of each element. Examples of the alloy include an Ag—Cu alloy and an Ag—Bi alloy. The layer 8 containing at least one of Ti, Ag, Cu, and Bi as a main component can be alloyed with Sn, and the melting point of the connection portion 14 can be lowered. If the melting point of the connection portion 14 is lowered, the heating temperature at the time of mounting the semiconductor element can be lowered to 250 ° C. or lower, so that the thermal stress generated by the heating at the time of mounting can be suppressed. The thickness of the layer 8 mainly composed of at least one of Ti, Ag, Cu, and Bi is preferably in the range of 0.5 to 1.5 μm.

The layer 8 mainly composed of at least one of Ti, Ag, Cu, and Bi is a layer mainly composed of Ti layer 8-1 and Ag, Cu, and Bi as shown in FIG. It may be a two-layer structure of 8-2. In addition, the lower layer (second diffusion prevention layer 5 side) is a Ti layer 8-1 and the upper layer (Au or Au—Sn alloy layer 9 side) is a layer mainly composed of at least one of Ag, Cu, and Bi. The structure which forms 8-2 is preferable. Since the Ti layer 8-1 has good wettability with the second diffusion preventing layer 5, the bonding strength can be improved.
For example, when forming an alloy film containing at least one of Ti, Ag, Cu, and Bi as a main component by vapor deposition or sputtering, a binary vapor deposition method in which two types are prepared as a vapor deposition source (or sputtering target) or an alloy in advance It is necessary to prepare a vaporized vapor deposition source (or alloy target). However, in an alloy containing two or more of Ti, Ag, Cu, and Bi, the deposition rate (or sputtering rate) of each element is different, so that it is difficult to form an alloy film having a target alloy composition. On the other hand, if it is the above two-layer structure, the method of forming with the film thickness which becomes the target alloy composition when it melt-mixes by heating can be used. In this case, since a two-layer structure can be formed by a method of forming one layer at a time using a deposition source (or sputtering target) of one kind of element, productivity is improved.

The second diffusion preventing layer 5 is present under the layer 8 containing at least one of Ti, Ag, Cu, and Bi as a main component. The second diffusion prevention layer 5 prevents the diffusion of elements between the conductor layer 4 and the layer 8 containing at least one of Ti, Ag, Cu, and Bi as a main component. As the material, for example, at least one selected from Pt, Pd, and Ni and alloys based on these are used as in the first diffusion preventing layer 3. The thickness of the second diffusion preventing layer 3 is preferably in the range of 0.05 to 0.4 μm, for example.
The second diffusion preventing layer 5 diffuses elements between the Au layer as the conductor layer 4 and the connection portion 14 including the layer 8 containing, for example, at least one of Ti, Ag, Cu, and Bi as a main component. It is to prevent. When Au in the conductor layer 4 diffuses into the layer 8, when the layers 8, 9, and 10 are mixed by heating during mounting, the Au-rich connection layer 13 is formed. When an Au-rich connection layer is formed, the bonding strength decreases.

  As described above, the wiring layer 12 includes the base metal layer 2, the first diffusion prevention layer 3, and the conductor layer 4, and the connection portion 14 includes at least the second diffusion prevention layer 5, Ti, Ag, Cu, and Bi. A ceramic wiring board having a layer 8 mainly composed of one kind, a layer 9 made of Au or Au—Sn alloy, and a solder layer 10 made of Sn or Sn alloy has Sn and Ti in the joint 13 when the semiconductor element is mounted. , Ag, Cu, and Bi, the generation of a large lump of Sn alloy composed of at least one kind can be suppressed. For example, the maximum diameter of the Sn alloy made of at least one of Sn and Ti, Ag, Cu, Bi can be made 1.5 μm or less. As a result, the Sn alloy grains composed of at least one of Sn and Ti, Ag, Cu, and Bi are dispersed in the connection portion 14 in a small dispersed state, and the stress applied to the interface between the Sn and Sn alloy can be dispersed small. Cracks are unlikely to occur at the interface between Sn and the Sn alloy, and the bonding of the semiconductor elements can be made stronger. In addition, when the bonding is strengthened, cracks are less likely to occur at the bonding portion even during operation of the semiconductor element. Therefore, it can be said that the semiconductor device of the present invention has improved reliability and operating characteristics.

  Here, in FIGS. 1 and 2, there is no particular problem if the horizontal size of the wiring portion 13 and the connecting portion 14 is “width of the wiring portion 13 ≧ width of the connecting portion 14”, and each is formed in a pattern shape. May be. In addition, the size in the width direction of the base metal layer 2, the first diffusion prevention layer 3, and the conductor layer 4 constituting the wiring portion 13 is also “width of the base metal layer 2 ≧ width of the first diffusion prevention layer 3 ≧ conductor layer” If there is a relationship of “width of 4”, there is no problem. The width of the connecting portion 14 in the horizontal direction is “the width of the second diffusion preventing layer 5 ≧ the width of the layer 8 mainly composed of at least one of Ti, Ag, Cu, and Bi ≧ Au or Au—Sn alloy layer. If there is a relationship of “width of 9 ≧ Sn or width of Sn alloy solder layer 10”, there is no problem.

Further, as a preferable form, “width of conductor layer 4 ≧ second diffusion preventing layer 5> width of layer 8 mainly composed of at least one of Ti, Ag, Cu, Bi ≧ Au or Au—Sn alloy layer 9 width ≧ Sn or Sn alloy solder layer 10 width ”. When “the second diffusion preventing layer 5> the width of the layer 8 containing at least one of Ti, Ag, Cu, and Bi as a main component”, the solder layer 10 wets and spreads by heating and melting at the time of joining a semiconductor element or the like. In this case, if there is the second diffusion prevention layer 5 wider than the solder layer 10, wetting and spreading of the solder layer 10 can be suppressed.
In other words, the wet spreading area of the solder layer 10 can be made only on the second diffusion prevention layer 5 having low wettability with respect to Sn alloy or the like. As a result, the reaction with the conductor layer 4 due to the wetting and spreading of the solder layer 10, the compositional variation of the Sn alloy and the melting point increase, and the melting failure (incomplete melting) due to the melting point increase of the Sn alloy can be suppressed. It becomes possible. Furthermore, since the variation in the height of the solder layer 10 is suppressed by limiting the wet spreading area of the solder layer 10, it is possible to prevent a position defect in the height direction of a semiconductor element or the like.

  The shape of the second diffusion preventing layer 5 is that the outer peripheral portion of the second diffusion preventing layer 5 protrudes from the end of the solder layer 10 in the range of 1 μm to 100 μm in order to obtain the effect of suppressing the expansion of the wet spreading area of the solder layer 10. preferable. If the amount of protrusion of the second diffusion preventing layer 5 from the end of the solder layer 10 is smaller than 1 μm, there is a possibility that the solder layer 10 will wet and spread beyond the second diffusion preventing layer 5 when the solder layer 10 is melted. Even though the amount of protrusion exceeds 100 μm, the effect of suppressing wetting and spreading does not change, but the width of the second diffusion preventing layer 5 is unnecessarily widened, which may hinder the increase in the density of wiring and electrodes. There is. The protrusion amount of the second diffusion preventing layer 5 is more preferably equal to or higher than the height of the solder layer 10. In consideration of the formation density of the connection portion 14 and the like, the amount of protrusion of the second diffusion preventing layer 10 is more preferably 50 μm or less.

  As an embodiment, the Au layer 11 may be provided on the solder layer 10 made of Sn or Sn alloy as shown in FIG. The Au layer 11 can prevent oxidation of the solder layer 10 made of Sn or Sn alloy.

  Next, a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. FIG. 5 shows a structural example of a laser device to which the semiconductor device of the present invention is applied. In FIG. 5, 30 is a two-wavelength laser diode. That is, the two-wavelength laser diode 30 includes, for example, a first light emitting element portion 31 having an emission wavelength of 650 nm and a second light emitting element portion 32 having an emission wavelength of 780 nm. The first and second light emitting element portions 31 and 32 are formed by crystal growth of a semiconductor layer or the like on the GaAs substrate 33, respectively. The first and second light emitting element portions 31 and 32 have electrodes 34 and 35, respectively. A common electrode 36 is formed on the back side of the GaAs substrate 33.

  Such a two-wavelength laser diode 30 is bonded and mounted on the ceramic wiring substrate 10 of the above-described embodiment. The ceramic wiring board 20 includes a first wiring layer 12A and a second wiring layer 12B, and includes a wiring part 13 and a connection part 14, respectively. An electrode 34 of the first light emitting element portion 31 is joined to the connection portion 14 of the first wiring layer 12A, and an electrode 35 of the second light emitting element portion 32 is joined to the connection portion 14 of the second wiring layer 12B. Are joined. These constitute a laser device to which the semiconductor device of the present invention is applied.

  In the laser device (semiconductor device) of the above-described embodiment, when the laser diode 30 is bonded and mounted on the ceramic wiring substrate 20, the generation of a large Sn alloy lump in the connection portion 14 can be suppressed. Accordingly, it is possible to firmly bond the laser diode 30 to the ceramic wiring substrate 20, and it is possible to prevent an increase in the resistance of the connecting portion 14 and an increase in the operating current of the laser diode 30 based thereon. That is, it is possible to provide a high-quality, high-reliability laser apparatus with high reproducibility.

Although FIG. 5 shows an embodiment in which a laser diode is applied as a semiconductor element bonded and mounted on a ceramic wiring board, the semiconductor device of the present invention is not limited to this, and various semiconductor elements are connected to ceramic wiring. It can be applied to a semiconductor device bonded and mounted on a substrate. The semiconductor element applied to the semiconductor device of the present invention is not limited, but is particularly effective for an optical semiconductor element such as a laser diode or a photodiode.
Although a manufacturing method is not specifically limited, The following are mentioned as an example of a preferable manufacturing method.
First, the base metal layer 2, the first diffusion prevention layer 3, and the conductor layer 4 constituting the wiring layer 12 are sequentially formed by sputtering. Next, if necessary, after opening the part which becomes the connection part 14 and apply | coating a resist, the 2nd diffusion prevention layer 5 is formed into a film by sputtering method.
Next, a layer 8 mainly composed of at least one of Ti, Ag, Cu, and Bi, a layer 9 made of Au or Au—Sn alloy, and a solder layer 10 made of Sn or Sn alloy are sequentially formed by vacuum deposition. To go.
If necessary, the Au layer 11 is formed on the solder layer 10 made of Sn or Sn alloy by a vacuum deposition method.
Thus, it is preferable to use a sputtering method or a vacuum evaporation method. In particular, the layer 8 mainly composed of at least one of Ti, Ag, Cu, and Bi, the layer 9 made of Au or Au—Sn alloy, and the solder layer 10 made of Sn or Sn alloy are melt-mixed by heating at the time of mounting the semiconductor element. Thus, a solder layer having a predetermined composition is formed. At this time, if the thickness of each layer is not uniform, the composition in the solder layer at the time of melt mixing will vary. When the composition is varied, large Sn alloy grains are likely to be formed in the thick portion of the layer 8 mainly composed of Ti, Ag or the like.
Further, when mounting the semiconductor element, the ceramic wiring substrate of the present invention is provided with the layer 8 containing at least one of Ti, Ag, Cu, and Bi as a main component, and therefore a layer made of Au or Au—Sn alloy. 9. Although the solder layer 10 made of Sn or Sn alloy is provided, the bonding temperature can be lowered to 300 ° C. or lower, and further to 250 ° C. or lower.

  Next, specific examples of the present invention and evaluation results thereof will be described.

Examples 1 to 12, Reference Example 1
First, an aluminum nitride sintered body substrate having a diameter of 75 mm and a height of 0.2 mm was prepared as the ceramic substrate 1. After the aluminum nitride substrate 1 is cleaned, a thickness of 0.5 as a conductor layer 4 is formed by sputtering from a 0.1 μm thick Ti film to a base metal layer 2, a 0.2 μm thick Pt film. A μm Au layer was laminated in order.

Next, a resist having a rectangular opening of 1 mm × 0.5 mm was formed on the conductor layer 4, and then a second diffusion preventing layer 5 made of a Pt film having a thickness of 0.2 μm was formed by sputtering.
On the upper surface of the second diffusion prevention layer 5, a layer 8 mainly composed of at least one of Ti, Ag, Cu, Bi shown in Table 1 by vacuum deposition, Au or Au-Sn alloy layer 9, Sn or An Sn alloy solder layer 10 was formed. Each of these samples was diced to a size of 2 mm × 2 mm and then subjected to characteristic evaluation described later.

Comparative Examples 1-3
Samples were prepared in the same manner as in Examples 1 to 12 and Reference Example 1 except that the formation of the Au or Au—Sn alloy layer 9 was omitted, and subjected to characteristic evaluation described later.
About each ceramic wiring board (each sample which shows a structure in Table 1) of Examples 1-12 mentioned above , Reference example 1, and Comparative Examples 1-3, the maximum diameter of Sn alloy grain in connection layer 13, and a semiconductor element Adhesion and bonding strength (shear strength) were measured and evaluated as follows.

[Maximum diameter of Sn alloy grain in connecting portion 14]
An enlarged photograph of the cross section of the connecting portion 14 after joining the semiconductor elements was taken with an SEM, and the longest diagonal line of the Sn alloy grains shown there was taken as the maximum diameter. In addition, the enlarged photograph measured 3 places of 50 micrometers x 50 micrometers.
[Adhesion with semiconductor elements]
After mounting the Si chip on the wiring board of each example, a shear test was performed in which a load was applied from the lateral direction of the Si chip. Six share tests were conducted for each case. In the shear test, when the adhesion is good, the fracture mode inside the Si chip is shown. At this time, since the fracture strength of Si depends on the material strength, the numerical value of the shear strength varies greatly. Therefore, the judgment of adhesion is judged as good adhesion when the Si fracture mode is shown with a value of a certain strength (1200 kgf for the size) or more, and all samples are good. A good sample was indicated by Δ, and a sample having two or less good samples was indicated by ×. The evaluation results are shown in Table 1 together with the average value of the shear strength.

As can be seen from Table 1, it was found that the ceramic wiring board according to the present example has good adhesion to the semiconductor element and high bonding strength (shear strength).
On the other hand, since the comparative example does not have the layer 9 made of Au or Au—Sn alloy, both the adhesion and the bonding strength were bad values.

Examples 14-16
The relationship between the width (a) of the second diffusion prevention layer 5 and the width (b) of the layer 8 mainly composed of at least one of Ti, Ag, Cu, and Bi with respect to the ceramic wiring board of Example 1 is shown. , (A) = (b) was Example 14, (a)-(b) = 10 μm was Example 15, and (a)-(b) = 40 μm was Example 16.
In the ceramic wiring board according to each example, the solder layer wettability test was performed. As a test, each ceramic wiring board was heated at 250 ° C. for 30 seconds without placing a semiconductor element, and then the wet spreading state of the solder layer was confirmed with a metal microscope (100 times).
At that time, compared with the initial state, Example 14 was 50 μm, and both Example 15 and Example 16 were 2 μm.
If the wetting and spreading state is small, it becomes difficult to cause a connection failure such as a height failure when the semiconductor element is mounted. Further, from the results of Example 15 and Example 16, it is understood that it is sufficient that (a)-(b) is 10 μm or more.

It is sectional drawing which shows the principal part structure of the ceramic wiring board by one Embodiment of this invention. It is sectional drawing which shows the modification of the ceramic wiring board shown in FIG. It is sectional drawing which shows the modification of the ceramic wiring board shown in FIG. It is sectional drawing which shows the principal part structure of the conventional ceramic wiring board. It is a figure which shows the structural example of the laser apparatus as one Embodiment of the semiconductor device of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Ceramic substrate 2 ... Underlying metal layer 3 ... 1st diffusion prevention layer 4 ... Conductive layer 5 ... 2nd diffusion prevention layer 6 ... Solder layer 7 ... Antioxidation layer 8 ... At least 1 of Ti, Ag, Cu, Bi Layer 8-1 mainly composed of seed ... Ti layer 8-2 ... Layer 9 mainly composed of at least one of Ag, Cu, Bi ... Layer 10 composed of Au or Au-Sn alloy ... From Sn or Sn alloy Solder layer 11 ... Au layer 12 ... wiring layer 13 ... wiring portion 14 ... connecting portion 20 ... ceramic wiring substrate 30 ... laser diodes 31, 32 ... light emitting element portions 34, 35 ... individual electrode 36 ... common electrode

Claims (9)

On the upper surface of the ceramic substrate, a base metal layer, a first diffusion prevention layer, a conductor layer, a second diffusion prevention layer, a Ti layer, a layer mainly composed of at least one of Ag, Cu, Bi, and Au or Au- A ceramic wiring board comprising a wiring layer in which a solder layer made of Sn alloy layer and Sn or Sn alloy is sequentially laminated. The ceramic wiring board according to claim 1, wherein a thickness of the Au or Au-Sn alloy layer is 0.05 µm or more and 0.5 µm or less. The ceramic wiring board according to claim 1 or 2, wherein the Au-Sn alloy contains 63% or more of Au. 3. The ceramic wiring board according to claim 1, wherein the first diffusion prevention layer and the second diffusion prevention layer are made of at least one of Pt, Pd, and Ni or an alloy based thereon. . 3. The ceramic wiring board according to claim 1, wherein the Sn alloy has an Sn content of 90 wt% or more. The Sn alloy is an Sn alloy containing at least one selected from Au, Ag, Al, Bi, Cu, Cr, Ga, Ge, Ni, Pt, Si, Ti, and Zn. 5. The ceramic wiring board according to 5.   The ceramic wiring board according to claim 5 or 6, wherein the solder layer comprises two or more Sn alloys having different compositions. The semiconductor device according to any one of claims 1 to claim 7, characterized in that mounting the semiconductor element via the solder layer. The semiconductor device according to claim 8 .
The semiconductor device is an optical semiconductor element.

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