JPS6286895A - Soldering of electronic part - Google Patents
Soldering of electronic partInfo
- Publication number
- JPS6286895A JPS6286895A JP22700085A JP22700085A JPS6286895A JP S6286895 A JPS6286895 A JP S6286895A JP 22700085 A JP22700085 A JP 22700085A JP 22700085 A JP22700085 A JP 22700085A JP S6286895 A JPS6286895 A JP S6286895A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- solder
- point solder
- high melting
- low melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は電子部品を低温度で回路基板に接合しかつ接合
部の信頼性を向上させるのに好適な電子部品のはんだ付
け方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for soldering electronic components suitable for joining electronic components to a circuit board at low temperatures and improving the reliability of the joint.
−〔発明の背景〕
従来の電子回路装置においては、量産性および信頼性の
点から電子部品をはんだで回路基板に接続する方法が多
く使用されている。- [Background of the Invention] In conventional electronic circuit devices, a method of connecting electronic components to a circuit board by soldering is often used from the viewpoint of mass productivity and reliability.
この方法は電子部品と回路基板との間に介挿したはんだ
を加熱溶融して端子のメタライズたとえばCu、Niな
どとはんだとの間に合金層を形成して接続している。こ
のさい、はんだ自身は冷却過程で合金組成の偏析および
欠陥が発生して伸びが小さな鋳造組織状態〔文献9日本
金属学会誌第49巻第1号(1985)第26頁乃至第
33頁参照〕となる。In this method, solder inserted between an electronic component and a circuit board is heated and melted to form an alloy layer between the solder and the terminal metallization, such as Cu or Ni, for connection. At this time, the solder itself is in a cast structure state in which the elongation is small due to segregation and defects in the alloy composition during the cooling process [Refer to Reference 9, Journal of the Japan Institute of Metals, Vol. 49, No. 1 (1985), pp. 26 to 33] becomes.
しか゛るにこの鋳造状態は外力に対して伸びが小さく不
均一な変形を発生するため、疲労特性が悪く使用中に種
々のストレスたとえば、電子部品と基板との熱膨張差に
基づく熱ストレスに対して比較的短時間ではんだが破壊
する問題があった。However, this cast state has low elongation and non-uniform deformation in response to external forces, so it has poor fatigue properties and is susceptible to various stresses during use, such as thermal stress due to the difference in thermal expansion between electronic components and substrates. On the other hand, there was a problem that the solder was destroyed in a relatively short period of time.
また従来たとえば特開昭54−50269号公報に記載
されているように、ダイオードパワートランジスタなど
の半導体チップを取付基板と基板との間のはんだの厚さ
の不均一および傾きを防止して信頼性の良い接合をする
ために高融点はんだを低融点はんだでサンドインチして
低融点はんだのみを溶融して接合する方法が提案されて
いる。In addition, as described in Japanese Patent Application Laid-Open No. 54-50269, it has been proposed to prevent unevenness and inclination of solder thickness between two substrates on which semiconductor chips such as diode power transistors are mounted, thereby improving reliability. In order to achieve a good bond, a method has been proposed in which a high melting point solder is sandwiched with a low melting point solder and only the low melting point solder is melted and bonded.
しかるに、この方法では良好な平坦度を得ることは可能
かも知れないが、その反面溶融する低融点はんだと溶融
しない高融点はんだの界面近傍が金属組織学的に非常に
脆い層となるため、その後の熱サイクルなどにおいて簡
単に破壊するという問題があった。However, although it may be possible to obtain good flatness with this method, on the other hand, the area near the interface between the melting low-melting point solder and the unmelting high-melting point solder becomes a metallographically very brittle layer. There was a problem that they were easily destroyed during thermal cycles.
さらに特開昭51−118372号公報に記載されてい
るようにシリコンダイオードと支持電極およびリード線
とのはんだ接合のさい、低融点のSnと高融点のpbと
を完全に溶融して接合することにより、接合界面に十分
なSnを供給して界面を高強度化し、かつ高温使用に耐
えられる高pb組成のはんだにする方法が提案されてい
る。Furthermore, as described in Japanese Unexamined Patent Publication No. 51-118372, when soldering a silicon diode, a support electrode, and a lead wire, low melting point Sn and high melting point PB must be completely melted and joined. Accordingly, a method has been proposed in which a sufficient amount of Sn is supplied to the bonding interface to increase the strength of the interface and to produce a solder with a high Pb composition that can withstand high-temperature use.
しかるにこの方法は前記最初に述べた方法と同様に鋳造
はんだ組織が全体にわたって形成されるため、使用中の
熱サイクルにより簡単に疲労破壊する問題があった。However, in this method, similar to the first method mentioned above, a cast solder structure is formed over the entire surface, so there is a problem that fatigue failure easily occurs due to thermal cycles during use.
本発明は前記従来の問題点を解決し、高信頼性のはんだ
接続を可能とする電子部品のはんだ付け方法を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for soldering electronic components that solves the above-mentioned conventional problems and enables highly reliable solder connections.
本発明は前記の目的を達成するため発明したもので、発
明に至る経緯はつぎのとおりである。The present invention was invented to achieve the above object, and the background to the invention is as follows.
すなわち、本願発明者は前記従来の問題点につき検討し
た結果、高P b−S nの高融点はんだに低融点の共
晶はんだを溶かして接合すると、溶融接合界面には第6
図に示すP b−S n合金状態図から明らかなように
pbとSnとが連続した斜線範囲のはんだ合金が連続し
て形成される。That is, as a result of studying the above-mentioned conventional problems, the present inventor found that when a low melting point eutectic solder is melted and bonded to a high Pb-Sn high melting point solder, a sixth
As is clear from the Pb-Sn alloy phase diagram shown in the figure, a solder alloy in the shaded range in which pb and Sn are continuous is formed continuously.
一方、鋳造したP b−S n合金の引張強度−伸び特
性は前記日本金属学会誌第49巻第1号(1985)第
28頁に記載されているようにpbの一次固溶体(αp
b)が共晶組織を除くその中間組成ではデンドライト(
D andrite)状組織の技量および粒界に硬く、
低融点のSnリッチ層が形成されるため、第7図に示す
ように非常に脆くなることが明らかになった。On the other hand, the tensile strength-elongation properties of the cast Pb-Sn alloy are determined by the primary solid solution of pb (αp
When b) has an intermediate composition excluding the eutectic structure, dendrites (
D andrite)-like structure and grain boundaries are hard;
It has become clear that the formation of a Sn-rich layer with a low melting point makes it extremely brittle, as shown in FIG.
このように低融点はんだと高融点はんだとの間に接合プ
ロセス上必ず形成される一次固溶体(αpb)と共晶組
織との間のその中間組織は非常に脆い性質を有している
ため、以後の熱サイクルおよび熱衝撃により脆化層から
破壊を発生する。Since the intermediate structure between the primary solid solution (αpb) and the eutectic structure, which is inevitably formed during the bonding process between low-melting point solder and high-melting point solder, has a very brittle property, Fracture occurs from the brittle layer due to thermal cycles and thermal shock.
そこで本発明は、この脆化した中間組織を防止するため
、低融点はんだ層を薄く、高融点はんだ層を厚く形成し
て溶融時に十分な未溶融高融点はんだが残り、かつ溶融
時あるいはその後の熱処理において低融点はんだと高融
点はんだとの間に形成される中間層Snが均一に高pb
で高融点なはんだ層に拡散するようにすなわち、高融点
側の一次固溶体(αpb)の組成になるように低融点は
んだと高融点はんだとの高さの比を設定したことを特徴
とするものである。Therefore, in order to prevent this brittle intermediate structure, the present invention forms a thin low melting point solder layer and a thick high melting point solder layer, so that sufficient unmelted high melting point solder remains during melting, and during melting or afterward. During heat treatment, the intermediate layer Sn formed between the low melting point solder and the high melting point solder is uniformly high in pb.
The height ratio of the low melting point solder and the high melting point solder is set so that the solder diffuses into the high melting point solder layer, that is, the composition of the primary solid solution (αpb) is on the high melting point side. It is.
以下、本発明の実施例を示す第1図乃至第5図により説
明する。Embodiments of the present invention will be explained below with reference to FIGS. 1 to 5, which show embodiments of the present invention.
第1図は本発明により作られた高融点はんだを半導体チ
ップと同一長さの半導体装置の接合部を示す断面図、第
2図は本発明により作られた複数個の高融点はんだから
なる半導体装置の接合部を示す断面図、第3図(a)乃
至(C)は本発明による半導体基板のはんだ付け方法を
説明するための第1図A部拡大断面図、第4図は高融点
はんだおよび低融点はんだの体積比とpb濃度との関係
の一例を示す図、第5図は高融点はんだおよび低融点は
んだの体積比とpb濃度との関係の他の一例を示す図、
第6図はP b−S n合金状態図、第7図は鋳造はん
だの代表的な応力−ひすみ曲線図、第8図は加工はんだ
の応力−ひすみ曲線図である。FIG. 1 is a cross-sectional view showing a junction of a semiconductor device having the same length as a semiconductor chip using high melting point solder made according to the present invention, and FIG. 3(a) to 3(C) are enlarged sectional views of part A in FIG. 1 for explaining the method of soldering a semiconductor substrate according to the present invention, and FIG. 4 is a cross-sectional view showing the joint part of the device. FIG. 5 is a diagram showing another example of the relationship between the volume ratio of high melting point solder and low melting point solder and PB concentration,
FIG. 6 is a Pb-Sn alloy state diagram, FIG. 7 is a typical stress-strain curve diagram of cast solder, and FIG. 8 is a stress-strain curve diagram of processed solder.
本発明は第1図および第2図に示す如く、半導体チップ
1と基板2との間に電極4,5を介して予じめ加工成形
され上下両端面に低融点の共晶はんだ(第3図に示す符
号6,7)を付着した高融点のはんだ3を介挿してこれ
ら低融点の共晶はんだのみを溶かして電極4,5と高融
点はんだ3とを拡散反応して溶融接合したのち、上記低
融点の共晶はんだの溶融温度かもしくは融点下の高温に
保持して接合部のSnを均一に拡散させて接合している
。As shown in FIGS. 1 and 2, the present invention is formed in advance by processing and forming between a semiconductor chip 1 and a substrate 2 through electrodes 4 and 5, and a low melting point eutectic solder (a third solder) is applied to both upper and lower end surfaces. After inserting the high melting point solder 3 with the symbols 6 and 7) shown in the figure and melting only the low melting point eutectic solder, the electrodes 4 and 5 and the high melting point solder 3 are melted and bonded through a diffusion reaction. The bonding is performed by maintaining the melting temperature of the low melting point eutectic solder or at a high temperature below the melting point to uniformly diffuse Sn in the bonding portion.
つぎに前記第1図および第2図に示す半導体基板の製造
プロセスについて第3図(a)乃至(C)により説明す
る。Next, the manufacturing process of the semiconductor substrate shown in FIGS. 1 and 2 will be explained with reference to FIGS. 3(a) to 3(C).
まず第3図(a)に示す如く各種の材料からなる基板2
上に各々の材料に適した方法で電極5を形成する。すな
わち、たとえば基板2がアルミナセラミックで形成され
ている場合には電極5をAg−pbおよびWなどの導体
ペーストを印刷・焼成して形成する。また基板2がSi
およびガラスで形成されている場合には、電極5をCr
−Cu 、 Cr−Cu−Ni、Ti−Cuなどの薄膜
を真空蒸着あるいはスパッタなどにより蒸着して形成す
る。この蒸着法は半導体チップ1側の電極4についても
使用される。First, as shown in FIG. 3(a), a substrate 2 made of various materials
Electrodes 5 are formed thereon using a method suitable for each material. That is, for example, when the substrate 2 is made of alumina ceramic, the electrode 5 is formed by printing and firing a conductive paste such as Ag-PB and W. Also, the substrate 2 is made of Si.
and if it is made of glass, the electrode 5 is made of Cr
A thin film of -Cu, Cr-Cu-Ni, Ti-Cu, etc. is deposited by vacuum evaporation or sputtering. This vapor deposition method is also used for the electrode 4 on the semiconductor chip 1 side.
このようにして形成された電極4,5上に低融点のはん
だたとえばP b−S nあるいはAu−5nなどの共
晶はんだもしくは純Snなどをはんだペーストの印刷、
リフ口あるいは板状に形成されたはんだ、はんだボール
、真空蒸着などによる供給、リフ口およびはんだディッ
プ(Dip)等により低融点はんだ層6,7を形成する
。なお本実施例においては上記低融点はんだ層6,7の
厚さを約30μmにしている。Printing a solder paste of low melting point solder such as eutectic solder such as Pb-Sn or Au-5n or pure Sn on the electrodes 4 and 5 thus formed;
The low melting point solder layers 6 and 7 are formed by supplying solder formed in a riff port or a plate shape, solder balls, vacuum evaporation, or by using a riff port or a solder dip (Dip). In this embodiment, the thickness of the low melting point solder layers 6 and 7 is approximately 30 μm.
つぎにこれら低融点はんだ層6,7間に上記電極4,5
と同様な形状に加工成形された高融点の加工はんだ3を
介挿する。この加工はんだ3はたとえば加工熱処理した
95すt%P b−5wt%Snを成形して使用する。Next, the electrodes 4 and 5 are placed between these low melting point solder layers 6 and 7.
A processed solder 3 having a high melting point and formed into a shape similar to the above is inserted. This processed solder 3 is used by molding, for example, 95%Pb-5wt%Sn that has been processed and heat treated.
上記加工・熱処理は溶解・鋳造して板状に圧延したのち
、90%圧下率まで加工して100℃で5時間不活性雰
囲気中で熱処理を行なったもので、このはんだの応力−
ひすみ曲線は第8図に示す加工材の応力−ひすみ曲線図
における■の特性に略一致しており、鋳造したままの応
力−ひすみ曲線図における95Pb特性に比較して伸び
が著しく改善されていることが理解される。The above processing and heat treatment involved melting, casting, rolling into a plate shape, processing to a reduction rate of 90%, and heat treatment at 100°C for 5 hours in an inert atmosphere.
The strain curve approximately corresponds to the characteristic marked ■ in the stress-strain curve diagram of the processed material shown in Figure 8, and the elongation is significantly improved compared to the 95Pb characteristic in the stress-strain curve diagram of the as-cast material. It is understood that what is being done.
このようにして低融点はんだ6,7間に高融点の加工・
熱処理した約1ma+程度の厚さの高融点はんだ3を介
挿し、第3図(a)の状態を得たのち、低融点はんだ6
,7の融点直上までの温度に加熱して第3図(b)を得
る。この場合、低融点はんだ6.7としてP b−S
nの共晶はんだを使用したときには、200℃の温度ま
で加熱している。なお、加熱初期において、低融点はん
だ6,7は電極4゜5と拡散9反応してSnと電極4,
5との間に固溶体および金属間化合物8たとえばCu電
極ならばCu、Sn、がまたNi電極ならばNi、Sn
が、さらにAg電極ならばAg3Snなどが生成する。In this way, high melting point processing and
After inserting the heat-treated high melting point solder 3 with a thickness of about 1 ma+ to obtain the state shown in FIG. 3(a), the low melting point solder 6 is inserted.
, 7 to a temperature just above the melting point to obtain the result shown in FIG. 3(b). In this case, P b-S is used as the low melting point solder 6.7
When n eutectic solder is used, it is heated to a temperature of 200°C. In addition, at the initial stage of heating, the low melting point solder 6, 7 reacts with the electrode 4.5 by diffusion 9 and forms Sn and the electrode 4,
5 and intermetallic compounds 8, for example, Cu and Sn for Cu electrodes, and Ni and Sn for Ni electrodes.
However, if it is an Ag electrode, Ag3Sn etc. will be generated.
一方、高融点の加工はんだ3とは反応・拡散領域に第6
図に示す如く、pbの一次固溶体(αpb)と共晶組織
との間に連続して中間層9が形成される。On the other hand, processed solder 3 with a high melting point has a 6th layer in the reaction/diffusion region.
As shown in the figure, an intermediate layer 9 is formed continuously between the primary solid solution of pb (αpb) and the eutectic structure.
さらに加熱を続けると、第3図(c)に示す如く約30
μmの低融点はんだ層6,7は電極4,5および加工は
んだ3と完全に反応して中間層9は殆んど消失し、殆ん
どpbの一次固溶体(αpb)となって接合界面には電
極4,5との反応層8のみが形成され、高融点はんだ3
と電極4,5との間に良好な接合部を形成することがで
きる。この場合の低融点のはんだ層6,7に対してpb
の一次固溶体(αPb)を形成するために必要な高融点
のはんだ3の体積は第4図に示す如く、各々のはんだを
均一に拡散混合させると、 95wt%P b−5wt
%Snのときには体積比が約8倍以上(同図■矢印)に
なる。また同図における良好なはんだ組成とは前記第7
図から明らかな如く軟かく伸びの優れた90wt%Pb
−10wt%Snより高pbな組成をいう。さらに第4
図では高融点はんだ3として98すt%pb−2vt%
Snの場合も示しているが、この場合には矢印■よりも
大きな体積比4.3以上必要である。If heating is continued further, approximately 30
The μm low melting point solder layers 6 and 7 completely react with the electrodes 4 and 5 and processed solder 3, and the intermediate layer 9 almost disappears, becoming almost a primary solid solution of PB (αpb) and forming the bonding interface. In this case, only the reaction layer 8 with the electrodes 4 and 5 is formed, and the high melting point solder 3
A good joint can be formed between the electrodes 4 and 5 and the electrodes 4 and 5. In this case, pb is used for the low melting point solder layers 6 and 7.
As shown in Figure 4, the volume of the high melting point solder 3 required to form the primary solid solution (αPb) is 95wt%Pb-5wt when each solder is uniformly diffused and mixed.
%Sn, the volume ratio becomes about 8 times or more (solid arrow in the figure). In addition, the good solder composition in the same figure means the seventh
As is clear from the figure, 90wt%Pb is soft and has excellent elongation.
- Refers to a composition with higher pb than 10wt%Sn. Furthermore, the fourth
In the figure, high melting point solder 3 is 98st%pb-2vt%
The case of Sn is also shown, but in this case a volume ratio of 4.3 or more is required, which is larger than the arrow ■.
前記加熱温度200℃における全加熱保持時間は約40
秒で行なったが、これよりも高温度で短時間で行ないう
ろことは云うまでもないところである。The total heating holding time at the heating temperature of 200°C is approximately 40
It was done in seconds, but it goes without saying that it was done at a higher temperature and in a shorter time.
また共晶はんだの融点直下で約150℃の熱処理のとき
には、約30分加熱保持することにより、上記の場合と
同様な拡散・反応を得ることができる。Further, when heat treatment is performed at about 150° C. just below the melting point of the eutectic solder, the same diffusion and reaction as in the above case can be obtained by holding the heat for about 30 minutes.
このようにして製作された第1図に示す半導体基板にお
いては、パワトランジスタを温度サイクル−55〜+1
50℃、1サイクル/hrの試験を行なって寿命を評価
すると、疲労寿命が従来の接合部に比較して約2〜5倍
向上することができた。In the semiconductor substrate shown in FIG. 1 manufactured in this way, the power transistor is subjected to a temperature cycle of -55 to +1.
When the lifespan was evaluated by conducting a test at 50° C. and 1 cycle/hr, it was found that the fatigue life was improved by about 2 to 5 times compared to conventional joints.
なお、上記の実施例においては、Pb−8n系のはんだ
を対象として述べたが、これに限定されるものでなく、
たとえばIn−Pb系、In−8n系。In addition, in the above-mentioned example, Pb-8n-based solder was described, but it is not limited to this.
For example, In-Pb type, In-8n type.
I n−P b−S n系などの材料においても同様の
効果を得ることができることは云うまでもない。It goes without saying that similar effects can be obtained with materials such as I n-P b-S n-based materials.
本発明は以上述べたる如く、硬くて伸びの小さな中間は
んだ層をなくすることができ、これによって均一なはん
だ接続を得ることができるから。As described above, the present invention makes it possible to eliminate the intermediate solder layer that is hard and has little elongation, thereby making it possible to obtain a uniform solder connection.
容易な操作で高信頼度の電子回路装置を得ることができ
、今後ますます高密度化および高信頼度化が要求される
面付実装分野の電子回路装置の高機能化に大きな貢献を
することができる効果を有する。It is possible to obtain highly reliable electronic circuit devices with easy operation, and to make a major contribution to the enhancement of the functionality of electronic circuit devices in the field of surface mounting, where higher density and higher reliability are required in the future. It has the effect of
【図面の簡単な説明】
第1図は本発明により作られた半導体装置を示す断面図
、第2図は本発明により作られた複数個の高融点はんだ
からなる半導体装置を示す断面図、第3図(a)乃至(
c)は本発明による半導体装置のはんだ付け方法を説明
するための第1図A部拡大断面図、第4図は高融点はん
だおよび低融点はんだの体積比とpb濃度との関係の一
例を示す図、第5図は高融点はんだおよび低融点はんだ
の体積比とpb濃度との関係の他の一例を示す図、第6
図はP b−S n合金状態図、第7図は鋳造はんだの
代表的な応力−ひすみ曲線図、第8図は加工はんだの応
力−ひすみ曲線図である。
1・・・半導体チップ、2・・・基板、3・・・高融点
はんだ、4,5・・・電極、6,7・・・低融点はんだ
層、8・・・金属間化合物、9・・・中間層。[Brief Description of the Drawings] Fig. 1 is a sectional view showing a semiconductor device made according to the present invention, Fig. 2 is a sectional view showing a semiconductor device made of a plurality of high melting point solders made according to the present invention, Figure 3 (a) to (
c) is an enlarged sectional view of part A in FIG. 1 for explaining the method of soldering a semiconductor device according to the present invention, and FIG. 4 shows an example of the relationship between the volume ratio of high melting point solder and low melting point solder and PB concentration. Figure 5 is a diagram showing another example of the relationship between the volume ratio of high melting point solder and low melting point solder and PB concentration, Figure 6
The figure is a phase diagram of a Pb-Sn alloy, FIG. 7 is a typical stress-strain curve diagram of cast solder, and FIG. 8 is a stress-strain curve diagram of processed solder. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Substrate, 3... High melting point solder, 4, 5... Electrode, 6, 7... Low melting point solder layer, 8... Intermetallic compound, 9... ...middle class.
Claims (1)
する電子部品のはんだ付け方法において、上記電子部品
および回路基板と、これらの間に介挿された加工成型後
の高融点はんだとの間に低融点はんだを付着し、これら
低融点はんだと高融点はんだの高さの比を予じめ設定し
て溶融時に十分な未溶融高融点はんだが残り、かつ溶融
時あるいはその後の熱処理のさい、低融点はんだと高融
点はんだとの間に形成される中間層が均一な高融点はん
だ層に拡大させたことを特徴とする電子部品のはんだ付
け方法。1. In a method of soldering electronic components such as semiconductors to a circuit board by soldering, between the electronic components and circuit board and the high melting point solder inserted between them after processing and molding. A low melting point solder is attached to the solder, and the height ratio of these low melting point solders and high melting point solders is set in advance so that sufficient unmelted high melting point solder remains during melting, and during melting or subsequent heat treatment. A method for soldering electronic components, characterized in that an intermediate layer formed between a low melting point solder and a high melting point solder is expanded into a uniform high melting point solder layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22700085A JPS6286895A (en) | 1985-10-14 | 1985-10-14 | Soldering of electronic part |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22700085A JPS6286895A (en) | 1985-10-14 | 1985-10-14 | Soldering of electronic part |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6286895A true JPS6286895A (en) | 1987-04-21 |
Family
ID=16853938
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22700085A Pending JPS6286895A (en) | 1985-10-14 | 1985-10-14 | Soldering of electronic part |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6286895A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011114338A (en) * | 2009-11-27 | 2011-06-09 | Ind Technol Res Inst | Die-bonding method of led chip, and led manufactured by the method |
JP2017054804A (en) * | 2015-09-11 | 2017-03-16 | Necスペーステクノロジー株式会社 | Lead solder joint structure and manufacturing method |
US9877399B2 (en) | 2015-09-11 | 2018-01-23 | Nec Space Technologies, Ltd. | Lead solder joint structure and manufacturing method thereof |
JP2020136331A (en) * | 2019-02-14 | 2020-08-31 | 株式会社日産アーク | Semiconductor device and manufacturing method thereof |
-
1985
- 1985-10-14 JP JP22700085A patent/JPS6286895A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011114338A (en) * | 2009-11-27 | 2011-06-09 | Ind Technol Res Inst | Die-bonding method of led chip, and led manufactured by the method |
JP2017054804A (en) * | 2015-09-11 | 2017-03-16 | Necスペーステクノロジー株式会社 | Lead solder joint structure and manufacturing method |
US9877399B2 (en) | 2015-09-11 | 2018-01-23 | Nec Space Technologies, Ltd. | Lead solder joint structure and manufacturing method thereof |
JP2020136331A (en) * | 2019-02-14 | 2020-08-31 | 株式会社日産アーク | Semiconductor device and manufacturing method thereof |
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