JPS56152353A - Receiving circuit of single current system - Google Patents
Receiving circuit of single current systemInfo
- Publication number
- JPS56152353A JPS56152353A JP5538380A JP5538380A JPS56152353A JP S56152353 A JPS56152353 A JP S56152353A JP 5538380 A JP5538380 A JP 5538380A JP 5538380 A JP5538380 A JP 5538380A JP S56152353 A JPS56152353 A JP S56152353A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- level
- binary
- analogue
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
- H04L25/062—Setting decision thresholds using feedforward techniques only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Small-Scale Networks (AREA)
Abstract
PURPOSE:To form the multidrop transmission system of 1:N physically, by determining the binary level of the receiving signal on a basis of the level of the analogue signal for decision and the level of the receiving signal. CONSTITUTION:Decision signal generating circuit 7 connected to the transmission line generates the analogue decision signal of the intermediate level of the binary receiving signal from the analogue binary signal transmitted through the trasmission line. Binary circuit 8 connected to the transmission line and circuit 7 discriminates which side of the analogue decision signal the level of the analogue binary receiving signal exists in, and a digital binary signal is generated. Clamp circuit 9 consists of circuit part UL for clamping of the upper limit level and circuit part LL for clamping of the lower limit level.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5538380A JPS56152353A (en) | 1980-04-28 | 1980-04-28 | Receiving circuit of single current system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5538380A JPS56152353A (en) | 1980-04-28 | 1980-04-28 | Receiving circuit of single current system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56152353A true JPS56152353A (en) | 1981-11-25 |
Family
ID=12996969
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5538380A Pending JPS56152353A (en) | 1980-04-28 | 1980-04-28 | Receiving circuit of single current system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56152353A (en) |
-
1980
- 1980-04-28 JP JP5538380A patent/JPS56152353A/en active Pending
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