JPS56156020A - Arithmetic processor - Google Patents
Arithmetic processorInfo
- Publication number
- JPS56156020A JPS56156020A JP5385580A JP5385580A JPS56156020A JP S56156020 A JPS56156020 A JP S56156020A JP 5385580 A JP5385580 A JP 5385580A JP 5385580 A JP5385580 A JP 5385580A JP S56156020 A JPS56156020 A JP S56156020A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- detector
- analog signal
- noninverse
- result
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To realize a detection of fault over a wide range, by installing a polarity inverter at the side of a detector to transmit a noninverse signal and an inverse signal alternately to the side of a processor and then deciding a normal state when the result of addition of said two signals is substantially zero. CONSTITUTION:The analog signal detected by a detector 1 is supplied to a switching circuit 10 in the form of the 1st analog signal AS1 of a noninverse signal and the 2nd analog signal AS2 of an inverse signal and then converted into the digital signals DS1 and DS2 through an A/D converter 2 to be delivered through a transmitter 5. A discriminator 12 adds the output of detector 1 to the data stored in the storage circuit 11 after a sampling to decide whether the result of addition is close to zero or not.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5385580A JPS56156020A (en) | 1980-04-22 | 1980-04-22 | Arithmetic processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5385580A JPS56156020A (en) | 1980-04-22 | 1980-04-22 | Arithmetic processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56156020A true JPS56156020A (en) | 1981-12-02 |
Family
ID=12954378
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5385580A Pending JPS56156020A (en) | 1980-04-22 | 1980-04-22 | Arithmetic processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56156020A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0758639A (en) * | 1993-07-05 | 1995-03-03 | Natl Sci Council | Inspection module structure of high resolution analog-to-digital converter |
JP2019110472A (en) * | 2017-12-19 | 2019-07-04 | トヨタ自動車株式会社 | A/d converter |
-
1980
- 1980-04-22 JP JP5385580A patent/JPS56156020A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0758639A (en) * | 1993-07-05 | 1995-03-03 | Natl Sci Council | Inspection module structure of high resolution analog-to-digital converter |
JP2019110472A (en) * | 2017-12-19 | 2019-07-04 | トヨタ自動車株式会社 | A/d converter |
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