JPS56143063A - Common storage protection system - Google Patents
Common storage protection systemInfo
- Publication number
- JPS56143063A JPS56143063A JP4447280A JP4447280A JPS56143063A JP S56143063 A JPS56143063 A JP S56143063A JP 4447280 A JP4447280 A JP 4447280A JP 4447280 A JP4447280 A JP 4447280A JP S56143063 A JPS56143063 A JP S56143063A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- write
- register
- protection
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To simplify the common memory protection management, by providing a plurality of interface IF devices connected to the common memory device with the memory protection lock memory individually and managing the memory independently. CONSTITUTION:The memory device 1 is commonly used for computers 3a-3c via IF devices 2a-2c. The computer 3 sets the write-in address to the address register 21 of the IF device 2, write-in data to the data register 22, and protection key at data write-in to the protection key register 23. The protection lock is read out from the protection lock memory 26 according to the content of the register 21, and the content of the register 23 is compared with it at the comparison circuit 25. As a result of comparison, if it is judged as write-in possible, the access to the device 1 is requested, and when the use of bus is permitted with the bus controller 4, data is written in the address set in the memory 15. If judged as write-in impossible the access request to the device 1 is inhibited, the write-in impossible signal is fed to the memory protection detecting circuit 24 and error is reported to the computer 3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4447280A JPS56143063A (en) | 1980-04-04 | 1980-04-04 | Common storage protection system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4447280A JPS56143063A (en) | 1980-04-04 | 1980-04-04 | Common storage protection system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56143063A true JPS56143063A (en) | 1981-11-07 |
Family
ID=12692450
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4447280A Pending JPS56143063A (en) | 1980-04-04 | 1980-04-04 | Common storage protection system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56143063A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01307851A (en) * | 1988-06-07 | 1989-12-12 | Fujitsu Ltd | Storage control system |
-
1980
- 1980-04-04 JP JP4447280A patent/JPS56143063A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01307851A (en) * | 1988-06-07 | 1989-12-12 | Fujitsu Ltd | Storage control system |
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