GB1536436A - Memory reconfiguration device - Google Patents

Abstract

1536436 Memory system INTERNATIONAL STANDARD ELECTRIC CORP 22 July 1976 [28 July 1975] 30603/76 Heading G4A A memory system for connection to one or more processors via respective buses includes a plurality of memory blocks each formed by a plurality of memory modules one of which is a spare, and a plurality of controllers, one for each memory block, each controller having means to store the address of a module and data indicating whether that module is to be replaced by the spare module and means responsive to a memory address and the stored data to select the addressed or the spare module as appropriate. As described the memory has 4 blocks (2 address bits), each of 16 modules (4 address bits), each storing 16 pages (4 address bits) each of 512 words (9 address bits). Each controller is accessed by the block address bits to store the access request, and a circuit selects the highest priority stored access request, the module and page address bits of which access a lock memory storing read and write memory protection keys (which may be different) for each page in the memory block. The address and the data supplied to or from the memory are parity checked, any error in either memory protection or parity causing the controller to send an error signal. The lock data may be accessed and modified by processor commands which can also cause a module address (4-bits) and a reconfiguration bit to be stored in a memory 61 when one of the modules is to be replaced by the spare module. The appropriate 4 bits of an incoming memory address AD15-AD18 are compared, 62, with the stored reconfiguration address and if the comparison is positive C, if the reconfiguration bit indicates replacement S, and if the memory is not undergoing refreshing SELR, the replacement module is selected, Sp. Otherwise the addressed module S00-S15 is selected. An arrangement is provided, 66, which in the presence of a command bit DI12, exchanges the two halves of an addressed module by selectively complementing the highest order page address bit A19.