GB2227861A - Data processing system - Google Patents

Abstract

A data processing system comprises a number of modules, interconnected by a bus 12. The operation of the system is monitored by a diagnostic processor. The diagnostic processor can send signals over the bus to cause any one of the modules to be isolated from the bus, preventing the module from transmitting data on to the bus. A module is also isolated in response to an internal failure signal or a reset signal. Similarly, the diagnostic processor can remove the isolation from a particular module by sending further signals over the bus. <IMAGE>

Description

Data Processing System This invention relates to data processing systems. More specifically, the invention is concerned with a data processing system comprising a plurality of modules interconnected by means of a bus.

In such a system, if one of the modules develops a fault, it is usually necessary to isolate that module from the bus, to prevent it from sending signals on the bus that would result in propagation of the fault to the rest of the system.

The object of the Invention is to provide novel way of isolating such a module.

Summary of the invention.

According to the Invention there is provided a data processing system comprising a plurality of modules Interconnected by a bus, wherein each module comprises: (a) driving means for ccnnecting signals from the module to the bus, (b) receiving means for receiving data and address signals from the bus, and (c) control means, operative upon receipt of a predetermined address value unique to the module, and a predetermined data value, for clsabling said driving means to prevent signals from the module froz being transmitted on to the bus.

Brief description of the drawings Figure 1 is a block diagram of a data processing system including a plurality of modules interconnected by a bus.

Figures 2 and 3 are block circuit diagrams showing logic in one of the modules for isolating that module from the bus.

Description of an embodiment of the invention One data processing system in accordance with the invention will now be described by way of example with reference to the accompanying drawings.

Referring to Figure 1, the system comprises a plurality of modules 10, and a diagnostic processor 11, interconnected by a bus 12.

The modules 10 may be processing units, peripheral controllers, or direct memory access (DMA) controllers. Each module comprises a circuit board, containing an on-board microprocessor or DATA controller, as well as on-board memory. The exact nature of each module forms no part of the present invention.

The bus 12 comprises DATA lines, ADDRESS lines, and CONTROL lines. In this particular example, it is assumed that the DATA and ADDRESS lines are separate.

However, it will be appreciated that in other embodiments of the invention these lines could be multiplexed together on to the same set of lines.

Referring now to Figure 2, each of the modules 10 contains logic as follows for controlling the connection of that module to the bus, and for isolating that module from the bus in the event of a failure.

The module includes three bus driver circuits 20, 21 and 22. Driver circuit 20 couples data from an internal data bus 23 on the board to the DATA lines of the system bus 12. Driver circuits 21 and 22 respectively couple address and control signals from the on-board microprocessor or DMA Controller (not shown) to the ADDRESS and CONTROL lines of the bus 12. The driver circuits 20, 21 and 22 are all enabled when a signal ENABLE : L is asserted. (The "L" indicates that a negative logic convention is used for this signal; that is, the signal is deemed to be asserted when it is at the lower of two voltage levels, and de-asserted when at the higher voltage level).

The module also includes two receiver circuits 24 and 25. Circuit 24 couples signals from the DATA lines of the bus 12 to the internal data bus 23 of the board. Circuit 25 couples signals from the ADDRESS lines of the bus 12 to an internal address path 26, for addressing an on-board memory (not shown). Both the receiver circuits 24, 25 have their enable inputs wired to a low voltage level, so that both are permanently enabled.

Each module also includes a decoder 27, connected to the internal address path 26, and arranged to recognise a predetermined control address value, unique to that module. When the decoder 27 recognises the predetermined address value, it asserts a signal SEL:L (i.e. causes thls signal to go low from its normally high level).

Referring now to Figure 3, the sIgnal ENABLE:L which enables the driver circuits 20, 21 and 22 is produced by a bistable (flip-flop.) circuit 28. When the bistable 28 is in its clear state, the signal ENABLE:L is asserted (low), and when the bistable 28 is in its SET state, the signal ENABLE:L is de-asserted (high).

The SET input of the bistable 28 15 connected to the output of an AND gate 29. The first input of this AND gate receives the output of an OR gate 30, which receives the signals SEL:L and DATA (0) (I.e. the least significant bit of the internal data bus 23). The second input of the AND gate 29 receives a control signal BRD-FAIL:L, which Is asserted when a failure ls detected internally within the module 10. The third input of the AND gate 29 receives a control signal RESET:L which is asserted when the module is reset (e.g.

by means of a reset button on the module).

The CLEAR input of the bistable 28 is connected to the output of a NAND gate 31. One input of this gate receives DATA(0) while the other input receives the inverse of the signal SEL:L Operation The operation of the logic shown in Figures 2 and 3 will now be described.

It is assumed that, initially, the module is operating normally and that ENABLE:L is asserted, so that the driver circuits 20, 21 and 22 are all enabled, allowing the module to send signals over the system bus 12.

In operation, the diagnostic processor 11 monitors the operation of all the modules 10. If it detects an error in operation, indicating a failure in one of the modules, the following action is taken.

The diagnostic processor places on the ADDRESS lines of the bus 12 the predetermined control address value corresponding to the faulty module. This address is detected by the decoder 27 in the faulty module, causing SEL:L to be asserted. At the same time, the diagnostic processor sets the least significant bit of the DATA lines to "zero", which makes DATA(0) low.

Since SEL:L and Data (0) are both low, the output of the OR gate 30 goes low, and this disables the AND gate 29. This in turn causes the bistable 28 to be set, de-asserting ENABLE:L. Thus, the driver circuits 20, 21 and 22 are disabled, preventing the module from transmitting any signals over the system bus 12, and thereby isolating the module from the bus. The module is similarly isolated if either of the signals BRD-FAIL:L or RESET:L is asserted.

Once the module has been isolated, it will remain in this condition until the isolation is removed by the diagnostic processor, as follows.

The diagnostic processor places on the ADDRESS lines the predetermined control address value of the module in question. This address is detected by the decoder 27, causing SEL:L to be asserted. At the same time, the disgnostic processor sets the least significant bit of the DATA lines to "one", which makes DATA(0) high.

Since SEL:L is low and DATA(0) is high, the NAND gate 31 is enabled, and this clears the bistable 28. Thus, ENABLE:L is asserted again, re-enabling the driver circuits 20, 21 and 22.

Claims (5)

1. A data processing system comprising a plurality of modules interconnected by a bus, wherein each module comprises: (a) driving means for connecting signals from the module to the bus, (b) receiving means for receiving data and address signals from the bus, and (c) control means, operative upon receipt of a predetermined address value unique to the module, and a predetermined data value, for disabling said driving means to prevent signals from the module from being transmitted on to the bus.

2. A system according to Claim 1 wherein the control means also disables the driving means in response to an internal failure signal in the module.

3. A system according to Claim 1 or 2 wherein the control means also disables the driving means in response to a reset signal in the module.

4. A system according to any preceding claim wherein the control means in each module is operative upon receipt of said predetermined address value and a further predetermined data value, to enable said driving means so as to allow signals from the module to be transmitted on to the bus.

5. A data processing system substantially as hereinbefore described with reference to the accompanylng drawings.